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order number: 315038-003us december 2007 intel ? 81348 i/o processor datasheet product features two integrated intel xscale ? processors 667 mhz, 800 mhz and 1.2 ghz arm* v5te compliant instruction/data cache: 32 kbyte, 4-way set associative, nru replacement algorithm, lockable unified level 2 cache: 512 kbyte set associative, nru replacement algorithm 128-entry branch target buffer 8-entry write buffer 8-entry fill and pend buffer internal bus 128-bit wide at 333 mhz and 400 mhz depending on processor speed can support either pci-x or pci express* as an endpoint can support both pci-x central resource and pci express* root complex support for pci express* lane widths of x1, x2, x4, x8 eight serial-attached scsi links also capable of supporting direct-attached sata targets integrated sram memory controller (1 mb); dedicated to the sas transport address translation unit 2 kb or 4 kb outbound read queue 4 kb outbound write queue 4 kb inbound read and write queue application dma controller three independent channels connected to the mcu and the south internal bus 4 kbyte data transfer queue crc 32c calculation performs optional xor on read data multi-ported memory controller intel xscale ? processor inputs and north internal bus, south internal bus and adma input ports pc3200 and pc4300 double data rate (ddr2 400, ddr2 533) up to 4 gb of 64-bit ddr2 400, ddr2 533 optional single-bit error correction, multi- bit detection ecc support supports registered and unbuffered ddr2 memory 36-bit addressable 32-bit memory support two programmable 32-bit timers and watchdog timer sixteen general purpose i/o pins eight activity/status pairs one per sas port three i 2 c bus interface units two uart (16550) units 64 byte receive and transmit fifos 4 pin master/slave capable peripheral bus interface 8-, 16-bit data bus with two chip selects 25 demultiplexed address lines interrupt controller unit four priority levels interrupt pending register vector generation 16 external interrupt pins with high priority interrupt (hpi#) 1357-ball, flip chip ball grid array (fcbga), 37.5 mm x 37.5 mm and 1.0 mm ball pitch
intel ? 81348 i/o processor datasheet december 2007 2 order number: 315038-003us leg al li nes and dis clai mers leg al li nes and dis clai mers information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intels terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear fac ility appli cations. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the a bsence or characteristics of any features or instructions marked reserved or undefined. intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the information here is subject to change without notice. d o not finalize a design with this information. the products described in this document may contain design defects or errors known as errata which may cause the product to dev iate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature, may be obtained by calling 1-800-548- 4725, or by visiting intels web site . intel processor numbers are not a measure of performance. processor numbers differentiate features within each processor family , not across different processor families. see http://www.intel.com/products/processor_number for details. code names are only for use by intel to identify products, platforms, programs, services, etc. (products) in development by i ntel that have not been made commercially available to the public, i.e., announced, launched or shipped. they are never to be used as commercial name s for products. also, they are not intended to function as trademarks. bunnypeople, celeron, celeron inside, centrino, centrino logo, core inside, flash file, i 960, instantip, intel, intel logo, intel386, intel486, intel740, inteldx2, inteldx4, intelsx2, intel core, intel inside, intel inside logo, intel. leap ahead., intel. leap ahead. logo, intel n etburst, intel netmerge, intel netstructure, intel singledriver, intel speedstep, intel strataflash, intel viiv, intel vpro, intel xscale, itanium, itanium in side, mcs, mmx, oplus, overdrive, pdcharm, pentium, pentium inside, skoool, sound mark, the journey inside, vtune, xeon, and xeon inside are trademark s of intel corporation in the u.s. and other countries. *other names and brands may be claimed as the property of others. copyright ? 2007, intel corporation. all rights reserved.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 3 contentsintel ? 81348 contents 1.0 introduction .............................................................................................................. 7 1.1 about this document........................................................................................... 7 1.1.1 terminology ............................................................................................ 7 1.1.2 other relevant documents ........................................................................ 7 2.0 features ....................................................................................................................9 2.1 about the intel? 81348 i/o processor ................................................................... 9 2.2 intel? 81348 i/o processor features ................................................................... 11 2.2.1 host interface........................................................................................ 11 2.2.2 internal busses ...................................................................................... 12 2.2.3 application dma controllers ..................................................................... 12 2.2.4 address translation unit ......................................................................... 12 2.2.5 messaging unit ...................................................................................... 12 2.2.6 ddr2 memory controller ......................................................................... 13 2.2.7 sram memory controller......................................................................... 13 2.2.8 peripheral bus interface .......................................................................... 13 2.2.9 i 2 c bus interface units ........................................................................... 13 2.2.10 uart units ............................................................................................ 13 2.2.11 interrupt controller unit.......................................................................... 13 2.2.12 xsi system controller............................................................................. 14 2.2.13 inter-processor communication................................................................ 14 2.2.14 timers .................................................................................................. 14 2.2.15 gpio .................................................................................................... 14 3.0 package information ............................................................................................... 15 3.1 package introduction ......................................................................................... 15 3.2 functional signal definitions ............................................................................... 15 3.2.1 signal pin descriptions ............................................................................ 15 4.0 electrical specifications ........................................................................................... 62 4.1 v ccpll pin requirements .................................................................................... 64 4.2 targeted dc specifications ................................................................................. 66 4.3 targeted ac specifications ................................................................................. 68 4.3.1 clock signal timings............................................................................... 68 4.3.2 ddr2 sdram interface signal timings...................................................... 71 4.3.3 peripheral bus interface signal timings ..................................................... 72 4.3.4 i 2 c/smbus interface signal timings.......................................................... 73 4.3.5 pci bus interface signal timings .............................................................. 74 4.3.6 pci express* differential transmitter (tx) output specifications ................... 75 4.3.7 pci express* differential receiver (rx) input specifications ......................... 77 4.3.8 boundary scan test signal timings .......................................................... 78 4.4 ac timing waveforms........................................................................................ 79 4.5 storage interface electrical specifications ............................................................. 88
intel ? 81348contents intel ? 81348 i/o processor datasheet december 2007 4 order number: 315038-003us figures 1 intel? 81348 i/o processor functional block diagram ...................................................10 2 1357-lead fcbga package (top and bottom views) .....................................................40 3 intel ? 81348 i/o processor balloutpackage top (left side) .........................................42 4 intel ? 81348 i/o processor balloutpackage top (right side) .......................................43 5 intel ? 81348 i/o processor balloutpackage bottom (left side) ................................. ...44 6 intel ? 81348 i/o processor balloutpackage bottom (right side) ..................................45 7 v cc3p3pllx low-pass filter .........................................................................................64 8 v cc1p2plls0 , v cc1p2plls1 low-pass filter ......................................................................65 9 v cc1p2plld , v cc1p2pllp low-pass filter.........................................................................65 10 clock timing measurement waveforms........................................................................79 11 output timing measurement waveforms .....................................................................80 12 input timing measurement waveforms........................................................................81 13 i 2 c interface signal timings ......................................................................................81 14 ddr2 sdram write timings ......................................................................................82 15 dqs falling edge output access time to/from m_ck rising edge ................................. ...82 16 ddr2 sdram read timings .......................................................................................83 17 ac test load for all signals except pci, pci-express and ddr2 and storage phy ............................................................................................................83 18 ac test load for ddr2 sdram signals........................................................................83 19 pci/pci-x tov(max) rising edge ac test load ............................................................84 20 pci/pci-x tov(max) falling edge ac test load............................................................84 21 pci/pci-x tov(min) ac test load ..............................................................................84 22 transmitter test load (100 ? diff load) ......................................................................84 23 transmitter eye diagram...........................................................................................85 24 receiver eye opening (differential).............................................................................85 25 pbi output timings...................................................................................................86 26 pbi external device timings (flash) ............................................................................87 27 maximum amplitude .................................................................................................89 28 intel? 81348 i/o processor storage phy 1.2 v/1.8 v power sequencing system requirements ...............................................................................................90
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 5 contentsintel ? 81348 tables 1 pin description nomenclature .................................................................................... 15 2 ddr2 sdram signals ............................................................................................... 16 3 peripheral bus interface signals................................................................................. 18 4 compact pci hot swap signals .................................................................................. 19 5 pci bus signals ....................................................................................................... 20 6 pci express* signals ................................................................................................ 23 7 storage interface signals .......................................................................................... 24 8 interrupt signals...................................................................................................... 27 9i 2 c and sm bus signals ............................................................................................ 28 10 uart signals........................................................................................................... 29 11 miscellaneous signals ............................................................................................... 31 12 power and ground signals......................................................................................... 32 13 reset strap signals .................................................................................................. 33 14 functional pin mode behavior .................................................................................... 36 15 intel ? 81348 i/o processor 1357-lead packagealphabetical ball listings ...................... 46 16 intel ? 81348 i/o processor 1357-lead packagealphabetical signal listings................... 54 17 absolute maximum ratings ....................................................................................... 62 18 operating conditions ................................................................................................ 63 19 dc characteristics.................................................................................................... 66 20 i cc characteristics.................................................................................................... 67 21 pci clock timings .................................................................................................... 68 22 pci express* clock timings ....................................................................................... 69 23 ddr2 output clock timings....................................................................................... 70 24 ddr2 sdram signal timings ..................................................................................... 71 25 peripheral bus interface signal timings....................................................................... 72 26 i 2 c/smbus signal timings ......................................................................................... 73 27 pci signal timings ................................................................................................... 74 28 pci express* rx input specifications .......................................................................... 75 29 pci express* tx output specifications ........................................................................ 76 30 pci express* rx input specifications .......................................................................... 77 31 boundary scan test signal timings ............................................................................ 78 32 ac measurement conditions ...................................................................................... 83 33 storage interface reference clock electrical characteristics [s_clkp0/s_clkn0] ............. 88 34 storage interface transmitter output electrical characteristics [s_txp[7:0] s_txn[7:0] ... 89 35 storage interface receiver input electrical characteristics [s_rxp[7:0] s_rxn[7:0] .......................................................................................... 90
intel ? 81348contents intel ? 81348 i/o processor datasheet december 2007 6 order number: 315038-003us revision history date revision description december 2007 003 revised for 4 gb memory support. april 2007 002 updated legal page 2 . edited text in section 2.2.2 . revise pcixcap description in ta b le 5 . updated ta b l e 1 9 for cgp, cpcix, cddr2 and lpin values. revised ta b l e 1 8 for tcase (tc) maximum value to 100c. revised figure 28 . october 2006 001 initial release.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 7 introductionintel ? 81348 1.0 introduction 1.1 about this document this document is a reference guide for the external architecture of the intel ? 81348 i/o processor (also known as the 81348). 1.1.1 terminology to aid the discussion of the 81348 architecture, the following terminology is used: downstream at or toward a pci bus with a higher number (after configuration) word 16 bits of data dword 32 bits of data qword 64 bits of data host processor processor located upstream from the 81348 local processor intel xscale ? processor within the 81348 local bus 81348 internal bus local memory memory subsystem on the intel xscale ? microarchitecture, ddr2 sdram or peripheral bus interface busses upstream at or toward a pci bus with a lower number (after configuration) 1.1.2 other relevant documents 1. intel xscale ? microarchitecture developers manual (order number 273473)intel corporation 2. pci local bus specification , revision 2.3pci special interest group 3. pci-x addendum to the pci local bus specification, revision 2.0apci special interest group 4. pci hot-plug specification, revision 1.0pci special interest group 5. pci bus power management interface specification , revision 1.1pci special interest group 6. pci express specification , revision 1.0apci special interest group
intel ? 81348introduction intel ? 81348 i/o processor datasheet december 2007 8 order number: 315038-003us
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 9 featuresintel ? 81348 2.0 features 2.1 about the intel ? 81348 i/o processor the 81348 is a single- or dual-function pci device that integrates two intel xscale ? processors with intelligent peripherals including a pci bus interface and eight serial- attached scsi (sas) engines. the 81348 also supports two internal busses: north xsi bus and south xsi bus. with the two internal busses, transactions can take place simultaneously on each bus. the north xsi bus provides the two intel xscale ? processors with low-latency access to either the ddr2 sdram memory controller, the on-chip sram memory controller, or the sas engines control registers. peripherals that generate large burst transactions are located on the south xsi bus, thus allowing the two intel xscale ? processors exclusive access to the north xsi bus. the 81348 consolidates the following features into a single system: ? two intel xscale ? processors running at speeds up to 1.2 ghz ? eight serial protocol links capable of serial-attached scsi (sas) or serial ata (sata) operation ? pciClocal memory bus address translation unit, function 0 programming interface ? messaging unit, function 0 programming interface ? application direct memory access (dma) controller (including offload for up to a 16-source xor operation) ? transport dma controllers ? peripheral bus interface unit ? integrated ddr2 memory controller ? integrated sram memory controller ? two programmable timers per intel xscale ? processor ? watchdog timer per intel xscale ? processor ? three i 2 c bus interface units ? two serial port units ? sixteen general-purpose input/output (gpio) ports ? activity/status pin pairsone per sas engine ? internal north busCsouth bus bridge it is an integrated processor that addresses the needs of intelligent i/o storage applications and helps reduce intelligent i/o system costs. the 81348 can support pci-x 1.0b and/or pci express* as a reset option. the pci bus is an industry standard, high-performance, low-latency system bus. the 81348 pci bus is capable of 133 mhz operation in pci-x 1.0b mode (as defined by the pci-x addendum to the local bus specification, revision 1.0b). also, the processor supports a 66 mhz conventional pci mode (as defined by the pci local bus specification , revision 2.3). the addition of the intel xscale ? processors brings intelligence to the pci bus application bridge. 81348 supports an x8 pci express* interface.
intel ? 81348features intel ? 81348 i/o processor datasheet december 2007 10 order number: 315038-003us the 81348 can be set up as a single- or dual-function pci device at reset using external straps. refer to the clocking and reset section in the intel ? 81348 i/o processor developers manual for a description of the reset options. when the 81348 is configured as a single-function device, the host programming interface is presented as the address translation unit (atu) and the messaging unit (mu). the mu provides the messaging interface between the host processor and the 81348. when the 81348 is configured as a dual-function device, pci function 0 host programming interface is presented as the atu with the mu. the reset strapping options determine how the controllers sas/sata ports are assigned to function 1 and function 0. both the address and data busses on the 81348 south xsi bus are byte-wise parity protected. all the peripherals connected to the south xsi bus can check and generate parity. figure 1 is a block diagram of the 81348. figure 1. intel ? 81348 i/o processor functional block diagram pci - x intel? 81348 i/o processor b6140 -01 16 -bit i/f i 2 c bus 7 2-bit i/f sas serial bus serial bus bridge multi - port ddr ii sdram memory controller three application dma channels host interface (atu, chap) two transport dma channels multi - port sram memory controller two uarts three i 2 c bus interface apb pbi unit (flash) sas 0 phy sas 1 phy sas 7 phy intel xscale? processor (core id = 0h) 512k l 2 cache timers intel xscale? processor ( core id = 1h) 512k l2 cache inter - core interrupt interrupt controller timers inter - core interrupt interrupt controller smbus unit smbus 128- bit south internal bus 128 - bit north internal bus sas serial bu s pci - e imu host interface (atu , chap)
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 11 featuresintel ? 81348 2.2 intel ? 81348 i/o processor features the 81348 combines two intel xscale ? processors with powerful new features to create an intelligent i/o storage processor. this single- or dual-function pci device is fully compliant with the pci-x addendum to the pci local bus specification, revision 2.0 and pci express specification , revision 1.0. features specific to 81348 include the following: the 81348 is based upon two intel xscale ? processors. the processor operates at a maximum frequency of 1.2 ghz. the instruction cache is 32 kbytes in size and is 4-way set associative. also, the processor includes a data cache that is 32 kbytes and is 4- way set associative. the intel xscale ? processors also support a unified 512-kbyte level 2 (l2) cache that is 8-way set associative. the 81348 includes sixteen general purpose i/o (gpio) pins, and eight activity/ status pin pairs which are used for sas links for activity and status indicators. each sas link uses one activity/status pin pair. note: the subsections that follow provide a brief overview of each feature. refer to the appropriate chapter in the intel? 81348 i/o processor developers manual for full technical descriptions. 2.2.1 host interface the 81348 can be set up as either a single- or dual-function pci device, providing pci- x or pci express* interface or both pci-x and pci express* interfaces. the pci interface is selected as a reset option. when set up as a single-function pci device, the address translation unit (atu) and the messaging unit (mu) provide the programming interface between the host processor and the 81348. when set up as a dual-function device, the atu and the mu provide the programming interface between the host processor and the 81348 for function 0, whereas the third-party messaging interface (tpmi) provides the programming interface between the host processor and the 81348 for function 1. the pci interface is selected as a reset option. ? address translation unit ? ddr2 sdram memory controller ? messaging unit ? transport dma controllers ? flash interface unit ? uart units ? chip architecture performance unit ? address and data bus parity protection ?i 2 c bus interface units ? inter-processor communication ? multi-port sram memory controller ? timers ? application dma controllers ? watchdog timers ? xsi system controller (north and south) ? eight sas link engines with integrated phys
intel ? 81348features intel ? 81348 i/o processor datasheet december 2007 12 order number: 315038-003us 2.2.2 internal busses the 81348 is built around two internal busses: north internal bus and south internal bus. the two busses use the same bus protocol. the north internal bus is 128 bits wide and operates at up to 400 mhz. the north bus connects the two intel xscale ? processors, which have direct access to the ddr2 sdram and sram. the intel xscale ? processors also have direct access to the sas/satafibre channel engine memory- mapped registers. the north xsi bus is designed to provide the two intel xscale ? processors with low-latency access. the south internal bus is 128 bits wide and operates at up to 400 mhz. the south xsi bus provides the data paths for burst transactions generated by the dmas. the south xsi bus internal address and data busses are parity-protected on a byte-wise basis. agents on the south xsi bus can generate and check address and data parity. the point-to-point interfaces between the agents and the ddr2 and sram memory controllers are also parity-protected on a byte-wise basis. note: internal busses run at 333mhz for 667mhz core speed. internal busses run at 400mhz for 800mhz and 1.2ghz core speeds. 2.2.3 application dma controllers there are three application dma controllers. the application dma controller is dual- portedwith one of its ports connected to the south xsi bus and the other port to the ddr2 sdram memory controller. this application dma controller allows low-latency, high-throughput data transfers between pci bus agents and the ddr2 memory. the dma controller also allows data transfer between ddr2 memory. the dma controller supports chaining and unaligned data transfers. it is programmable through the intel xscale ? processor and the host processor. in addition to simple data transfers, the adma performs xor operations with up to 16 sources. 2.2.4 address translation unit the address translation unit (atu) allows pci transactions direct access to the 81348 local memory. the atu provides interface for the raid controller pci function. the atu supports transactions between pci address space and the 81348 address space. address translation is controlled through programmable registers accessible from both the pci interface and the intel xscale ? processor. dual access to registers allows flexibility in mapping the two address spaces. the atu also supports the following extended capability configuration headers: 1. power management header, as defined by pci bus power management interface specification , revision 1.1. 2. message signaled interrupt capability structure, as specified in pci local bus specification , revision 2.3. 3. pci-x capabilities list item, as specified in the pci-x addendum to the local bus specification, revision 1.0b.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 13 featuresintel ? 81348 2.2.5 messaging unit the messaging unit (mu) provides data transfer between the pci system and the 81348. it uses interrupts to notify each system when new data arrives. the mu has four messaging mechanisms: message registers, doorbell registers, circular queues, and index registers. each allows a host processor or external pci device and the 81348 to communicate through message passing and interrupt generation. the mu, in conjunction with the atu, exists as the pci interface for pci function 0 when function 0 is set up as a raid controller. 2.2.6 ddr2 memory controller the ddr2 memory controller allows direct control of the 400/533 mhz ddr2 sdram memory subsystem. it features programmable chip selects and support for error- correction codes (ecc). the ddr2 memory controller is multi-ported with the following interfaces: south internal bus, adma controllers, north internal bus. the memory controller interface configuration support includes unbuffered dimms, registered dimms, and discrete ddr2 sdram devices. 2.2.7 sram memory controller the sram memory controller allows direct control of a 1.0 mbyte sram memory subsystem. it supports error correction codes (ecc). the sram memory controller is ported with the following port: north internal bus. 2.2.8 peripheral bus interface the peripheral bus interface unit is a data communication path to the flash memory components or other peripherals of a 81348 hardware system. the pbi includes support for either 8- or 16-bit devices. to perform these tasks at high bandwidth, the bus features a burst-transfer capability which allows successive 8/16-bit data transfers. 2.2.9 i 2 c bus interface units there are three i 2 c (inter-integrated circuit) bus interface units that allow the intel xscale ? processor to serve as a master and slave device residing on the i 2 c bus. the i 2 c0 allows the i/o processor to interface to a storage enclosure processor, sep. for more information, refer to i 2 c peripherals for microcontrollers (philips semiconductor) 1 . 2.2.10 uart units the 81348 includes two uart units. the uart unit allow the two intel xscale ? processors to serve as a master and slave device residing on the uart bus. the uart units use a serial bus consisting of a two-pin interface. uart0 allows the 81348 to interface to a console port for debugging. also refer to the national semiconductor* 16550 device specification 2 . 1. http://www.semiconductors.philips.com/buses/i2c/ 2. http://www.national.com/pf/pc/pc16550d.html
intel ? 81348features intel ? 81348 i/o processor datasheet december 2007 14 order number: 315038-003us 2.2.11 interrupt controller unit each intel xscale ? processor supports an interrupt controller unit (icu). the icu aggregates interrupt sources both external and internal sources of the 81348 to the intel xscale ? processor. the icu supports high-performance interrupt processing with direct interrupt service routine vector generation on a per-source basis. each source has programmability for masking, processor interrupt input, and priority. 2.2.12 xsi system controller each xsi bus (north and south) employs an xsi system controller. the xsi system controller observes all the address or data bus requests from requestors and completors connected to the xsi bus. the xsi system controller handles xsi address bus arbitration, xsi data bus arbitration, framing address bus cycles, and framing data bus cycles. the xsi system controller provides the shared address and shared data paths from/to units. 2.2.13 inter-processor communication each intel xscale ? processor can interrupt or issue a reset to the second intel xscale ? processor. each processor can generate up to 32 interrupts to the second processor. 2.2.14 timers the 81348 supports two programmable 32-bit timers per processor. the 81348 also supports one watchdog timer per processor. 2.2.15 gpio the 81348 includes sixteen general-purpose i/o (gpio) pins, and eight activity/ status pin pairs.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 15 package informationintel ? 81348 3.0 package information 3.1 package introduction the 81348 is offered in a 1357-ball fcbga5 package. 3.2 functional signal definitions this section defines the pins and signals. 3.2.1 signal pin descriptions table 1. pin description nomenclature symbol description i input pin only o output pin only i/o pin can be either an input or an output od open-drain pin pwr power pin gnd ground pin pin must be connected as described sync(...) synchronous. signal meets timings relative to a clock. ? sync(p): synchronous to p_clkin ? sync(m): synchronous to m_ck[2:0] / m_ck#[2:0] ? sync(t): synchronous to tck async asynchronous. inputs can be asynchronous relative to all clocks. all asynchronous signals are level-sensitive. r/w indicates read or write capability. rst(p) the pin is reset with warm_rst# or p_rst# . rst(m) the pin is reset with m_rst# . m_rst# is asserted when the memory subsystem is reset. rst(pb) the pin is reset with pb_rstout# . pb_rstout# is asserted when the peripheral bus interface subsystem is reset. rst(t) the pin is reset with trst# . actlow the pin is an active-low signal. diff the pin is a differential signal pair. ? p at the end of a differential pin name indicates positive. ? n at the end of a differential pin name indicates negative.
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 16 order number: 315038-003us table 2. ddr2 sdram signals (sheet 1 of 2) name count type description m_ck[2:0] , m_ck#[2:0] 6 o diff memory clockout: is used to provide the three differential clock pairs to the unbuffered dimm for the external sdram memory subsystem. registered dimms use only the m_ck[0] / m_ck#[0] pair, which drives the input to the on-dimm pll. m_rst# 1 o async actlow memory reset: indicates that the memory subsystem has been reset. it is used to re-initialize registered dimms. ma[14:0] a 14 o sync(m) rst(m) memory address bus: carries the multiplexed row and column addresses to the sdram memory banks. auto-precharge is not supported. ba[2:0] 3 o sync(m) rst(m) sdram bank address: controls which of the internal banks to read or write. ba[1:0] are used for 512 mbit technology memory. ba[2:0] are used for 1 gbit technology memory. ras# 1 o sync(m) rst(m) actlow sdram row address strobe: indicates the presence of a valid row address on the multiplexed address bus ma[13:0] . cas# 1 o sync(m) rst(m) actlow sdram column address strobe: indicates the presence of a valid column address on the multiplexed address bus ma[13:0] . we# 1 o sync(m) rst(m) actlow sdram write enable: indicates whether the current memory transaction is a read or write operation. cs[1:0]# 2 o sync(m) rst(m) actlow sdram chip select: enables the sdram devices for a memory access. one for each physical bank. cke[1:0] 2 o sync(m) rst(m) sdram clock enable enables: the clocks for the sdram memory. deasserting places the sdram in self-refresh mode. one for each physical bank. dq[63:0] 64 i/o sync(m) rst(m) sdram data bus: carries 64-bit data to and from memory. during the data cycle, read or write data is present on one or more contiguous bytes. during write operations, unused pins drive to determinate values. cb[7:0] 8 i/o sync(m) rst(m) sdram ecc check bits: carry the 8-bit ecc code to and from memory during data cycles. dqs[8:0] , dqs#[8:0] 18 i/o sync(m) rst(m) diff sdram data strobes: carry differential or single-ended strobe signals, output in write mode, and input in read mode for source synchronous data transfer. dm[8:0] 9 o sync(m) rst(m) sdram data mask: controls which bytes on the data bus are to be written. when dm[8:0] is asserted, the sdram devices do not accept valid data from the byte lanes. m_vref 1i sdram voltage reference: is used to supply the input switching reference voltage for the memory input signals. odt[1:0] 2 o sync(m) rst(m) on-die termination: is used to turn on sdram on-die termination during writes.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 17 package informationintel ? 81348 m_cal[0] 1o memory calibration: connected to an external calibration resistor. memory output drivers reference the resistor to dynamically adjust drive strength to compensate for temperature and voltage variations. this pin connected through a 24.9 ? 1% resistor to ground. m_cal[1] 1o memory calibration: connected to an external calibration resistor. memory output drivers reference the resistor to dynamically adjust odt resistance to compensate for temperature and voltage variations. this pin connected through a 301 ? 1% resistor to ground. to t a l 1 3 5 a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin is nc. table 2. ddr2 sdram signals (sheet 2 of 2) name count type description
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 18 order number: 315038-003us table 3. peripheral bus interface signals name count type description a[24:0] 25 o rst(pb) peripheral address bus: carries the address bits for the current access. the pbi interface can address up to 32 mbytes. d[15:0] 16 i/o rst(pb) peripheral data bus: carries read or write data to and from memory. during write operations to 8-bit wide memory regions, the pbi drives unused bus pins to determinate values. poe# 1 o rst(pb) actlow peripheral output enable: indicates whether bus access is write or read with respect to i/o processor and is valid during entire bus access. this pin can be used to control output enable on a peripheral device. 0 = read 1 = write pwe# 1 o rst(pb) actlow peripheral write enable: indicates to the peripheral device whether or not to write data to the addressed space. this pin can be used to control the write enable on the peripheral device. 0 = write 1 = read pce[1:0]# 2 o rst(pb) actlow peripheral chip enable: specifies which of the two memory address ranges are associated with the current bus access. the pin remains valid during the entire bus access. note: these pins must be pulled up to v cc3p3 with external 8.2k ? 5%, 1/16 ? resistors for proper operation. pb_rstout# 1 o actlow peripheral bus reset out: can be used to reset the peripheral device. it has the same timing as the internal bus reset. to t a l 4 6
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 19 package informationintel ? 81348 table 4. compact pci hot swap signals name count type description hs_enum# 1 od rst(p) actlow hot swap event: conditionally asserted to notify system host that either a board has been freshly inserted or is about to be extracted. this signal informs the system host that the configuration of the system has changed. the system host then performs any necessary maintenance such as installing or quiesing a device driver. hs_lstat 1 i rst(p) hot swap latch status: input indicating state of the ejector switch. 0 = indicates the ejector switch is closed. 1 = indicates the ejector switch is open. if compact pci hot swap not supported, tie this signal low. hs_led_out 1 o rst(p) hot swap led output: outputs a logic one to illuminate the hot swap blue led. hs_freq[1:0] / cr_freq[1:0] 2 i/o rst(p) hot swap frequency: in hot swap mode, these pins are inputs, determining the bus frequency and mode during a pci-x hot swap event. these are valid only when pcix_ep# =0 and hs_sm# =0. 00 =133 mhz pci-x 01 =100 mhz pci-x 10 = 66 mhz pci-x 11 = 33 or 66 mhz. pci (frequency depends on p_m66en ) central resource frequency: while in central resource mode, these pins are outputs, which control the external pci-x clock generator. these are valid only when pcix_ep# =1. 00 = 133 mhz 01 =100 mhz 10 =66 mhz 11 =33 mhz ? these pins have internal pull-ups. to t a l 5
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 20 order number: 315038-003us table 5. pci bus signals (sheet 1 of 3) name count type description p_ad[63:32] 32 i/o sync(p) rst(p) pci address/data: is the upper 32 bits of the pci data bus driven during the data phase. p_ad[31:0] 32 i/o sync(p) rst(p) pci address/data: is the multiplexed pci address and lower 32 bits of the data bus. p_cbe[7]# 1 i/o sync(p) rst(p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[6]# 1 i/o sync(p) rst(p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[5]# 1 i/o sync(p) rst(p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[4]# 1 i/o sync(p) rst(p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[3]# 1 i/o sync(p) rst(p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[2]# 1 i/o sync(p) rst(p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[1]# 1 i/o sync(p) rst(p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_cbe[0]# 1 i/o sync(p) rst(p) actlow pci bus command and byte enables: are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables. p_par64 1 i/o sync(p) rst(p) pci bus upper dword parity is even parity across p_ad[63:32] and p_cbe_#[7:4]. p_req64# 1 i/o sync(p) rst(p) actlow pci bus request 64-bit transfer indicates the attempt of a 64-bit transaction on the pci bus. when the target is 64-bit capable, the target acknowledges the attempt with the assertion of p_ack64_#. p_ack64# 1 i/o sync(p) rst(p) actlow pci bus acknowledge 64-bit transfer indicates that the device has positively decoded its address as the target of the current access and the target is willing to transfer data using the full 64- bit data bus.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 21 package informationintel ? 81348 p_par 1 i/o sync(p) rst(p) pci bus parity is even parity across p_ad[31:0] and p_cbe_#[3:0]. p_frame# 1 i/o sync(p) rst(p) actlow pci bus cycle frame is asserted to indicate the beginning and duration of an access. p_irdy# 1 i/o sync(p) rst(p) actlow pci bus initiator ready indicates the initiating agents ability to complete the current data phase of the transaction. during a write, it indicates that valid data is present on the address/data bus. during a read, it indicates that the processor is ready to accept the data. p_trdy# 1 i/o sync(p) rst(p) actlow pci bus target ready indicates the target agents ability to complete the current data phase of the transaction. during a read, it indicates that valid data is present on the address/data bus. during a write, it indicates that the target is ready to accept the data. p_stop# 1 i/o sync(p) rst(p) actlow pci bus stop indicates a request to stop the current transaction on the pci bus. p_devsel# 1 i/o sync(p) rst(p) actlow pci bus device select is driven by a target agent that has successfully decoded the address. as an input, it indicates whether or not an agent has been selected. p_serr# 1 i/o od sync(p) rst(p) actlow pci bus system error is driven for address parity errors on the pci bus. p_rstout# 1 o async actlow pci reset out is based on p_rst# and warm_rst# . it brings pci-specific registers, sequencers, and signals to a consistent state. when either p_rst# or warm_rst# is asserted, it causes p_rstout# to assert and: ? pci output signals are driven to a known consistent state. ? pci bus interface output signals are three-stated. ? open-drain signals such as p_serr_# are floated. p_rstout# can be asynchronous to p_clk when asserted or deasserted. p_perr# 1 i/o sync(p) rst(p) actlow pci bus parity error is asserted when a data parity error occurs during a pci bus transaction. p_m66en 1 i pci bus 66 mhz enable indicates the speed of the pci bus. when this signal is sampled high, the pci bus speed is 66 mhz; when low, the bus speed is 33 mhz. p_idsel 1 i sync(p) pci bus initialization device select is used to select the 81348 during a configuration read or write. note: in central resource mode this pin must be pulled down to v ss with an external 4.7k ? 5%, 1/16 ? resistor for proper operation. table 5. pci bus signals (sheet 2 of 3) name count type description
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 22 order number: 315038-003us p_gnt[0]# / p_req# 1 o sync(p) actlow pci bus grant: ? internal arbiter mode: this is one of four output grant signals from the internal arbiter. pci bus request: ? external arbiter mode: this is the output request signal for the atu. p_req[0]# / p_gnt# 1 i sync(p) rst(p) actlow pci bus request: ? internal arbiter mode: this is one of four input request signals to the internal arbiter. pci bus grant: ? external arbiter mode: this is the input grant signal to the atu. p_gnt[3:1]# 3 o sync(p) actlow pci bus grant: ? external arbiter mode: not used ? internal arbiter mode: these are three of four output grant signals from the internal arbiter. p_req[3:1]# 3 i sync(p) rst(p) actlow pci bus request: ? external arbiter mode: not used ? internal arbiter mode: these are three of four input request signals to the internal arbiter. p_pcixcap 1 i pci-x capability: refer to the intel ? 81348 i/o processor specification update for more details. p_bmi 1 o sync(p) rst(p) pci bus master indicator indicates that the i/o processor is mastering a transaction on the pci bus. p_cal[0] 1 o pci calibration is connected to an external calibration resistor. the v ccvio pci output drivers reference the resistor to dynamically adjust the drive strength to compensate for voltage and temperature variations. this pin is connected through a 22.1 ? 1% resistor to ground. p_cal[1] 1 o pci calibration is connected to an external calibration resistor. the pci output drivers reference the resistor to dynamically adjust the odt resistance to compensate for voltage and temperature variations. this pin is connected through a 121 ? 1% resistor to ground. p_cal[2] 1 o pci calibration is connected to an external calibration resistor. the v cc3p3 pci output drivers reference the resistor to dynamically adjust the drive strength to compensate for voltage and temperature variations. this pin is connected through a 22.1 ? 1% resistor to ground. p_clkin 1 i pci bus input clock provides the ac timing reference for all pci transactions. p_clkout 1 o pci bus output clock: when refclkn / refclkp are used, the i/o processor can generate the pci output clocks. this pin is then connected to p_clkin and trace length matched to p_clko[3:0] . p_clko[3:0] 4 o pci bus output clocks: when refclkn / refclkp are used, the i/o processor can generate the pci output clocks. these pins then provide the pci clocks to devices on the pci bus. to t a l 1 0 5 table 5. pci bus signals (sheet 3 of 3) name count type description
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 23 package informationintel ? 81348 table 6. pci express signals name count type description refclkp , refclkn 2 i diff pci express* clock is the 100 mhz differential input reference clock for the pci express* interface. petp[7:0] , petn[7:0] 16 o diff pci express* transmit carries the differential output serial data and embedded clock for the pci express* interface. perp[7:0] , pern[7:0] 16 i diff pci express* receive carries the differential input serial data and embedded clock for the pci express* interface. pe_calp , pe_caln 2 i/o pci express* calibration pins are connected to an external calibration resistor. the pci express* output drivers can reference the resistor to dynamically adjust their slew rate and drive strength to compensate for voltage and temperature variations. a 1.4k ? 1% resistor is connected between these two pins. to t a l 3 6
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 24 order number: 315038-003us table 7. storage interface signals (sheet 1 of 3) name count type description s_clkn0 , s_clkp0 2 i diff storage clock is the 125 mhz 100 ppm differential input reference clock for the interface. note: should be ac coupled with a 100nf capacitor. s_txp[7:0] , s_txn[7:0] 16 o diff storage transmit carries the differential output serial data and embedded clock for the interface. note: should be ac coupled with a 10nf capacitor. s_rxp[7:0] , s_rxn[7:0] 16 i diff storage receive carries the differential input serial data and embedded clock for the interface. note: should be ac coupled with a 10nf capacitor. rbias[1:0] 2o resistor bias: a 6.49k ? 1% 1/8 ? external resistor must be connected between this pin and ground for proper operation. this resistor generates internal bias currents. rbias_sense[ 1:0] 2i/o resistor bias sense is used internally to sense ground. this ball must be connected to the same physical ground point as the rbias[1:0] resistor is connected to on the pcb. s_act0 / sclock0 1od storage activity: when sgpio[0] is disabled, this pin can be used to drive an led to indicate activity on the link for storage engine[0]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. serial clock: (default) when sgpio[0] is enabled, this pin is the serial output clock running at 99.8 khz. the falling edge of sclock0 is used to latch sload0 , sdataout0 , and sdatain0 . s_stat0 / sload0 1od storage status: when sgpio[0] is disabled this pin can be used to drive an led to indicate status of the link for storage engine[0]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. serial load: (default) when sgpio[0] is enabled, this pin is the serial load clock. it is driven high to indicate the start of the bit stream. s_act1 1od storage activity: when sgpio[0] is disabled, this pin can be used to drive an led to indicate activity on the link for storage engine[1]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. s_stat1 1od storage status: when sgpio[0] is disabled, this pin can be used to drive an led to indicate status of the link for storage engine[1]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. s_act2 / sdatain0 1od storage activity: when sgpio[0] is disabled, this pin can be used to drive an led to indicate activity on the link for storage engine[2]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. serial data in: (default) when sgpio[0] is enabled, this pin is the serial input data. there are three bits of data per device and up to eight devices are supported. s_stat2 / sdataout0 1od storage status: when sgpio[0] is disabled, this pin can be used to drive an led to indicate status of the link for storage engine[2]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. serial data out: (default) when sgpio[0] is enabled, this pin is the serial output data. there are three bits of data per device and up to eight devices are supported.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 25 package informationintel ? 81348 s_act3 1od storage activity: when sgpio[0] is disabled, this pin can be used to drive an led to indicate activity on the link for storage engine[3]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. s_stat3 1od storage status: when sgpio[0] is disabled, this pin can be used to drive an led to indicate status of the link for storage engine[3]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. s_act4 / sclock1 1od storage activity: when sgpio[1] is disabled, this pin can be used to drive an led to indicate activity on the link for storage engine[4]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. serial clock: (default) when sgpio[1] is enabled this pin is the serial output clock running at 99.8 khz. the falling edge of sclock1 is used to latch sload1 , sdataout1 and sdatain1 . s_stat4 / sload1 1od storage status: when sgpio[1] is disabled, this pin can be used to drive an led to indicate status of the link for storage engine[4]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. serial load: (default) when sgpio[1] is enabled, this pin is the serial load clock. it is driven high to indicate the start of the bit stream. s_act5 1od storage activity: when sgpio[1] is disabled, this pin can be used to drive an led to indicate activity on the link for storage engine[5]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. s_stat5 1od storage status: when sgpio[1] is disabled, this pin can be used to drive an led to indicate status of the link for storage engine[5]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. s_act6 / sdatain1 1od storage activity: when sgpio[1] is disabled, this pin can be used to drive an led to indicate activity on the link for storage engine[6]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. serial data in: (default) when sgpio[1] is enabled, this pin is the serial input data. there are three bits of data per device and up to eight devices are supported. s_stat6 / sdataout1 1od storage status: when sgpio[1] is disabled, this pin can be used to drive an led to indicate status of the link for storage engine[6]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. serial data out: (default) when sgpio[1] is enabled, this pin is the serial output data. there are three bits of data per device and up to eight devices are supported. table 7. storage interface signals (sheet 2 of 3) name count type description
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 26 order number: 315038-003us s_act7 1od storage activity: when sgpio[1] is disabled, this pin can be used to drive an led to indicate activity on the link for storage engine[7]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. s_stat7 1od storage status: when sgpio[1] is disabled, this pin can be used to drive an led to indicate status of the link for storage engine[7]. the pin can be direct driven by the storage engine or driven from an sgpio. note: connect the led to a series resistor pulled up to vcc. to t a l 5 4 table 7. storage interface signals (sheet 3 of 3) name count type description
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 27 package informationintel ? 81348 table 8. interrupt signals name count type description p_int[d:a]# / xint[3:0]# / gpio[11:8] 4 od i i/o async rst(p) actlow when pcix_ep# = 0: ? pci interrupt requests an interrupt from the central resource. the assertion and deassertion is asynchronous. a device asserts its xint[3:0]# / p_int[d:a]# line when requesting attention from its device driver. as soon as the xint[3:0]# / p_int[d:a]# signal is asserted, it remains asserted until the device driver clears the pending request. when pcix_ep# = 1: ? external interrupt requests are used by external devices to request interrupt service. these pins are level-detect inputs and are internally synchronized. these pins go to the xint[3:0]# inputs of the interrupt controller. the interrupt controller can steer the interrupt to either the fiq or the irq internal interrupt input of the intel xscale ? processor. general purpose i/o pins can be selected on a per-pin basis as general-purpose inputs or outputs. the default mode is a general- purpose input. xint[7:4]# / gpio[15:12] 4 i i/o async actlow external interrupt requests are used by external devices to request interrupt service. these pins are level-detect and are internally synchronized. these pins go to the xint[7:4]# inputs of the interrupt controller. the interrupt controller can steer the interrupt to either the fiq or the irq internal interrupt input of the intel xscale ? processor. general purpose i/o pins can be selected on a per-pin basis as general-purpose inputs or outputs. the default mode is a general- purpose input. gpio[7:0] / xint[15:8]# / pmonout 8 i/o i o async rst(p) general purpose i/o pins can be selected on a per-pin basis as general-purpose inputs or outputs. the default mode is a general- purpose input. external interrupts are used by external devices to request interrupt service. these pins are level-detect and are internally synchronized. these pins go to the xint[15:8]# inputs of the interrupt controller. these interrupts are dedicated to the intel xscale ? processor. to enable a given pin as an interrupt, it needs to be unmasked in the intctl[3:0] register. performance monitor out: the pmon unit output indicator generates a signal on the gpio[7] pin when enabled in the pmonen register. when enabled it will override the normal gpio[7] function. hpi# 1 i async actlow high-priority interrupt causes a high-priority interrupt to the i/o processor. this pin is level-detect only and is internally synchronized. nmi0# 1 i async actlow non-maskable interrupt causes a non-maskable data abort to the intel xscale ? processor 0 in the i/o processor. this pin is falling edge-detect only and is internally synchronized. nmi1# 1 i async actlow non-maskable interrupt causes a non-maskable data abort to the intel xscale ? processor 1 in the i/o processor. this pin is falling edge-detect only and is internally synchronized. to t a l 1 9
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 28 order number: 315038-003us table 9. i 2 c and sm bus signals name count type description scl0 1 i/o od i 2 c 0 clock provides synchronous operation of the i 2 c bus. sda0 1 i/o od i 2 c 0 data is used for data transfer and arbitration of the i 2 c bus. scl1 1 i/o od i 2 c 1 clock provides synchronous operation of the i 2 c bus. sda1 1 i/o od i 2 c 1 data is used for data transfer and arbitration of the i 2 c bus. scl2 1 i/o od i 2 c 2 clock provides synchronous operation of the i 2 c bus. sda2 1 i/o od i 2 c 2 data is used for data transfer and arbitration of the i 2 c bus. smbclk 1 i/o od sm bus clock provides synchronous operation of the sm bus. smbdat 1 i/o od sm bus data is used for data transfer and arbitration of the bus. to t a l 8 note: open drain outputs require an external pull-up resistor to pull up the signal to 3.3 v. the value of the pull-up resistor depends on the bus loading.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 29 package informationintel ? 81348 table 10. uart signals (sheet 1 of 2) name count type description u0_rxd 1 i async uart 0 serial input: serial data input from device pin to the receive shift register. u0_txd 1 o async uart 0 serial output: composite serial data output to the communications link-peripheral, modem, or data set. the txd signal is set to the marking (logic 1) state upon a reset operation. u0_cts# 1 i actlow async uart 0 clear to send: when low, this pin indicates that the receiving uart is ready to receive data. when the receiving uart deasserts cts# high, the transmitting uart must stop transmission to prevent overflow of the receiving uart buffer. the cts# signal is a modem-status input whose condition can be tested by the host processor or by the uart when in autoflow mode as described below: non-autoflow mode: when not in autoflow mode, bit[4] (cts) of the modem status register (msr) indicates the state of cts#. bit[4] is the complement of the cts# signal. bit[0] (dcts) of the modem status register indicates whether the cts# input has changed state since the previous reading of the modem status register. cts# has no effect on the transmitter. the user can program the uart to interrupt the processor when dcts changes state. the programmer can then stall the outgoing data stream by starving the transmit fifo or disabling the uart with the ier register. note: when uart transmission is stalled by disabling the uart, the user does not receive an msr interrupt when cts# reasserts. this is because disabling the uart also disables interrupts. to work around this, the user can use auto cts in autoflow mode, or program the cts# pin to interrupt. autoflow mode: in autoflow mode, the uart transmit circuity checks the state of cts# before transmitting each byte. when cts# is high, no data is transmitted. u0_rts# 1 o actlow async uart 0 request to send: this bit indicates to the remote device whether the uart is ready to receive data. when this bit is low, the uart is ready to receive data. a reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. non-autoflow mode: the rts# output signal can be asserted by setting bit[1] (rts) of the modem control register to 1. the rts bit is the complement of the rts# signal. autoflow mode: rts# is automatically asserted by the autoflow circuitry when the receive buffer exceeds its programmed threshold. it is deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold. u1_rxd 1 i async uart 1 serial input: serial data input from the device pin to the receive shift register.
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 30 order number: 315038-003us u1_txd 1 o async uart 1 serial output: composite serial data output to the communications link-peripheral, modem, or data set. the txd signal is set to the marking (logic 1) state upon a reset operation. u1_cts# 1 i actlow async uart 1 clear to send: when low, this pin indicates that the receiving uart is ready to receive data. when the receiving uart deasserts cts# high, the transmitting uart must stop transmission to prevent overflow of the receiving uart buffer. the cts# signal is a modem-status input whose condition can be tested by the host processor or by the uart when in autoflow mode as described below: non-autoflow mode: when not in autoflow mode, bit[4] (cts) of the modem status register (msr) indicates the state of cts#. bit[4] is the complement of the cts# signal. bit[0] (dcts) of the modem status register indicates whether the cts# input has changed state since the previous reading of the modem status register. cts# has no effect on the transmitter. the user can program the uart to interrupt the processor when dcts changes state. the programmer can then stall the outgoing datastream by starving the transmit fifo or disabling the uart with the ier register. note: when uart transmission is stalled by disabling the uart, the user does not receive an msr interrupt when cts# reasserts. this is because disabling the uart also disables interrupts. to get around this, the user can use auto cts in autoflow mode, or program the cts# pin to interrupt. autoflow mode: note: in autoflow mode, the uart transmit circuity checks the state of cts# before transmitting each byte. when cts# is high, no data is transmitted. u1_rts# 1 o actlow async uart 1 request to send: this bit indicates to the remote device whether the uart is ready to receive data. when low, the uart is ready to receive data. a reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. non-autoflow mode: the rts# output signal can be asserted by setting bit[1] (rts) of the modem control register to 1. the rts bit is the complement of the rts# signal. autoflow mode: rts# is automatically asserted by the autoflow circuitry when the receive buffer exceeds its programmed threshold. it is deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold. to t a l 8 table 10. uart signals (sheet 2 of 2) name count type description
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 31 package informationintel ? 81348 table 11. miscellaneous signals name count type description tck 1i test clock provides clock input for ieee 1149.1 boundary scan testing (jtag). state information and data are clocked into the device on the rising clock edge, and data is clocked out on the falling clock edge. tdi 1 i sync(t) test data input is the jtag serial input pin. tdi is sampled on the rising edge of tck, during the shift-ir and shift-dr states of the test access port. this signal has a weak internal pull-up to ensure proper operation when this pin is not being driven. tdo 1 o sync(t) rst(t) test data output is the serial output pin for the jtag feature. tdo is driven on the falling edge of tck during the shift-ir and shift- dr states of the test access port. at other times, tdo floats. the behavior of tdo is independent of other resets. trst# 1 i async actlow test reset asynchronously resets the test access port controller function of ieee 1149 boundary scan testing (jtag). this pin has a weak internal pull-up. note: this pin must be tied low when not used. tms 1 i sync(t) test mode select is sampled on the rising edge of tck to select the operation of the test logic for ieee 1149 boundary scan testing. this pin has a weak internal pull-up. nc 54 i/o no connect: pins have no usable function and must not be connected to any signal, power, or ground. p_rst# 1 i async actlow cold reset is used to asynchronously reset the i/o processor when it is low. this signal must be asserted whenever the power supplies are outside of the specified ranges. ? registers are reset to default values. ? pins are driven to known states. ? sticky configuration bits are reset. warm_rst# 1i async actlow warm reset is the same as a cold reset, except sticky configuration bits are not reset. this pin should only be used when the sticky bit functionality is required. in this scenario, the warm_rst# pin must be tied to the system reset pci_rst# signal while the p_rst# pin can be tied to the system power good signal. if the sticky bit functionality is not required, the warm_rst# pin should not be used and must be tied to vcc. when the pci express interface is used as an endpoint, the pci express inband hot reset mechanism can also be used to provide the sticky bit functionality. note: driving warm_rst# using any other methods than suggested above may result in unpredictable behavior of the device. thermda 1 i thermal diode anode is the anode of the thermal diode. thermdc 1 o thermal diode cathode is the cathode of the thermal diode. pur1 1i pull-up required 1: this pin must be pulled up to v cc3p3 with an external 8.2k ? 5%, 1/16 ? resistor for proper operation. to t a l 6 4
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 32 order number: 315038-003us table 12. power and ground signals name count type description v cc1p2plls0 1 pwr v cc pll storage: ball connected to a 1.2 v filtered board supply. provides power to one of two plls that control storage interface. v cc1p2plls1 1 pwr v cc pll storage: ball connected to a 1.2 v filtered board supply. provides power to one of two plls that control storage interface. v cc1p2pllp 1 pwr v cc pll pci-x: ball connected to a 1.2 v filtered board supply. provides power to pll that controls the pci-x logic and interface. v cc1p2plld 1 pwr v cc pll ddr: ball connected to a 1.2 v filtered board supply. provides power to the pll that controls the ddr2 sdram interface and processor digital logic. v cc3p3pllx 1 pwr v cc pll x: ball to be connected to a 3.3 v filtered board supply. this pin provides power to a voltage regulator, which supplies power to the pll that controls the intel xscale ? processor and xsi processor logic. vssplls0 1 gnd v ss pll storage: ball to be connected to a board ground plane at the location of the v cc1p2plls0 filter. vssplls1 1 gnd v ss pll storage: ball to be connected to a board ground plane at the location of the v cc1p2plls1 filter. vsspllp 1 gnd v ss pll pci-x: ball connected to capacitor of the v cc1p2pllp filter. vssplld 1 gnd v ss pll ddr2 sdram: ball connected to capacitor of v cc1p2plld filter. vsspllx 1 gnd v ss pll x: ball connected to capacitor of v cc3p3pllx filter. v cc1p2 187 pwr 1.2 v power: balls to be connected to a 1.2 v board power plane. these pins provide power to the processor logic. v cc1p2ae 8 pwr 1.2 v power: balls to be connected to a 1.2 v board power plane. these pins provide power to the pci express* analog logic. v cc1p2e 6 pwr 1.2 v power: balls to be connected to a 1.2 v board power plane. these pins provide power to the pci express* digital logic. v cc1p2ds 6 pwr 1.2 v power: balls to be connected to a 1.2 v board power plane. these pins provide power to the storage interface digital logic. v cc1p2as 9 pwr 1.2 v power: balls to be connected to a 1.2 v board power plane. these pins provide power to the storage interface analog logic. v cc1p2x 119 pwr 1.2 v power: balls to be connected to a 1.2 v board power plane. these pins provide power to the intel xscale ? processors. v ccvio 21 pwr vio power: balls to be connected to a 3.3v board power plane. these pins provide 3.3 v power to the pci-x i/os. v cc1p8 30 pwr 1.8 v power: balls to be connected to a 1.8 v board power plane. these pins provide power to the ddr2 sdram interface i/os. v cc1p8e 14 pwr 1.8 v power: balls to be connected to a 1.8 v board power plane. these pins provide power to the pci express* interface i/os. v cc1p8s 6 pwr 1.8 v power: balls to be connected to a 1.8 v board power plane. these pins provide power to the storage interface i/os. v cc3p3 42 pwr 3.3 v power: balls to be connected to a 3.3 v board power plane. these pins provide power to the pbi, miscellaneous pins, and pci-x i/os in mode 1. v ss 373 gnd ground: balls to be connected to a board ground plane. v sse 20 gnd pci express* ground: balls connected to a board ground plane. v ssas 20 gnd analog storage ground: balls connected to a board ground plane. v ssds 6 gnd digital storage ground: balls connected to a board ground plane. to t a l 8 7 7
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 33 package informationintel ? 81348 table 13. reset strap signals (sheet 1 of 3) name count type description boot_width_8# 1 reset strap pbi boot bus width: sets the default bus width for the pbi memory boot window. 0 = 8 bits wide 1 = 16 bits wide (default mode) note: muxed onto signal a[0] . df_sel[2:0] 3 reset strap device function select: these straps select the number of storage ports assigned to each function within 81348. note: df_sel[2] muxed onto signal a[9] note: df_sel[1] muxed onto signal a[8] note: df_sel[0] muxed onto signal a[7] see the device function select of the intel? 81348 i/o processor developer's manual for additional details. cfg_cycle_en# 1 reset strap configuration cycle enable: determines whether pci interface retries configuration cycles until configuration cycle retry bit is cleared in atu (pcsr[2] and host lockout bit is cleared. 0 = configuration cycles enabled 1 = configuration retry enabled (default mode) ? pci-x interface: configuration cycles are claimed and terminated with a retry status. ? pci express* interface: configuration requests result in a completion tlp with configuration retry status (crs). note: muxed onto signal a[1] hold_x0_in_rst# 1 reset strap hold intel xscale ? microprocessor 0 in reset: determines whether the intel xscale ? microprocessor number 0 is held in reset until the reset bit is cleared in the pci configuration and status register. 0 = hold in reset 1 = do not hold in reset (default mode) note: muxed onto signal a[2] hold_x1_in_rst# 1 reset strap hold intel xscale ? microprocessor 1 in reset: determines whether the intel xscale ? microprocessor number 1 is held in reset until the reset bit is cleared in the pci configuration and status register. 0 = hold in reset 1 = do not hold in reset (default mode) note: muxed onto signal a[3] mem_freq[1:0] 2 reset strap memory frequency: determines frequency at which ddr2 memory subsystem runs. 00 = reserved 01 =reserved 10 =533 mhz 11 =400 mhz (default mode) note: mem_freq[1] muxed onto signal a[5] note: mem_freq[0] muxed onto signal a[4] ext_arb# 1 reset strap external arbiter: determines whether the pci interface enables the integrated arbiter, or use an external arbiter. 0 = external arbiter 1 = internal arbiter (default mode) note: muxed onto signal a[6] interface_sel_pcix# 1 reset strap 0 = pci-x is active 1 = pci express is active (default mode) when both interfaces are active, this strap selects the atu that is function 0 in the internal address map. note: muxed onto signal a[10] pcix_ep# 1 reset strap pci-x end point: determines whether the pci-x interface operates as an endpoint or a central resource. 0 = endpoint 1 = central resource (default mode) note: muxed onto signal a[11] note: setting both pcix_ep# and pcie_rc# to endpoint is unsupported.
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 34 order number: 315038-003us pcie_rc# 1 reset strap pci-e root complex: determines whether pci express* interface operates as an endpoint or a root complex. 0 = root complex 1 = endpoint (default mode) note: muxed onto signal a[12] setting both pcix_ep# and pcie_rc# to endpoint is unsupported. smb_a5 , smb_a3 , smb_a2 , smb_a1 4 reset strap sm bus address: maps to address bit[5], bit[3], bit[2], and bit[1] where bits[7:0] represent address smbus slave port responds to when access is attempted. 0 = address bit is low 1 = address bit is high (default mode) note: smb_a5 muxed onto signal a[16] note: smb_a3 muxed onto signal a[15] note: smb_a2 muxed onto signal a[14] note: smb_a1 muxed onto signal a[13] pcix_pullup# 1 reset strap pci-x pull up: determines whether pci interface has on-die pull-ups enabled. these may be used for the central resource bus keepers. 0 = enable pci pull-up resistors 1 = disable pci pull-up resistors (default mode) note: muxed onto signal a[17] pcix_32bit# 1 reset strap 32-bit pci-x bus: indicates width of the pci-x bus to pci-x status register. enables pull-ups for upper half of bus when in 32-bit mode. 0 = 32-bit wide pci-x bus 1 = 64-bit wide pci-x bus (default mode) note: muxed onto signal a[18] pcixm1_100# 1 reset strap pci-x mode 1 100 mhz enable: in central resource mode, this bit limits pci-x bus to 100 mhz while in mode 1: 0 = limit pci-x mode 1 to 100 mhz 1 = 133 mhz enabled (default mode) note: muxed onto signal a[19] hs_sm# 1 reset strap hot swap startup mode: in end point mode, this bit determines whether hot swap mode is enabled. 0 = hot swap mode enabled 1 = hot swap mode disabled (default mode) note: muxed onto signal a[21] fw_timer_off# 1 reset strap firmware timer off: disables 400 ms firmware timer for development and debug. when enabled, timer automatically clears configuration cycle retry (ccr) bit in pcsr after 400 ms regardless of processor state. when disabled, ccr bit functions as normal based on state of cfg_cycle_en# pin at rising edge of p_rst#. 0 = firmware timer disabled 1 = firmware timer enabled (default mode) note: muxed onto signal a[22] controller_only# 1 reset strap controller-only enable: 0 = controller only, raid disabled 1 = raid enabled (default mode) note: muxed onto signal a[23] lk_dn_rst_bypass# 1 reset strap link down reset bypass: disables the full chip reset that would normally be caused by a link down or hot reset. 0 = do not reset on link down 1 = reset on link down (default mode) note: muxed onto signal a[24] table 13. reset strap signals (sheet 2 of 3) name count type description
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 35 package informationintel ? 81348 clk_src_pcie# 1 reset strap clock source pci-e: selects pci express* refclk pair as the input clock to the plls that control most internal logic. 0 = source clock is refclkp / refclkn 1 = source clock is p_clkin (default mode) note: when p_clko[3:0] are used this pin must be pulled low. note: muxed onto signal pwe# total 25 reset strap signals are latched on the rising edge of p_rst# . all reset strap signals are internally pulled to logic 1 by default. an external 4.7k ohm 5%, 1/16 ohm pull-down resistor is required to force a logic 0 on these pins. table 13. reset strap signals (sheet 3 of 3) name count type description
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 36 order number: 315038-003us table 14. functional pin mode behavior (sheet 1 of 4) pin b o u n d a r y s c a n h i g h z r e s e t ( e n d p o i n t ) r e s e t ( c e n t r a l r e s o u r c e ) n o r m a l 3 2 - b i t s d r a m p c i x _ 3 2 b i t # p c i x _ p u l l u p # w h e n o n l y p c i - x i n t e r f a c e a c t i v e w h e n o n l y p c i e x p r e s s * i n t e r f a c e a c t i v e m_ck[2:0] , m_ck#[2:0] zvovovoCCCCC m_rst# z0*0*voCCCCC ma[14:0] a zvovovoCCCCC ba[2:0] zvovovoCCCCC ras# zvovovoCCCCC cas# zvovovoCCCCC we# zvovovoCCCCC cs[1:0]# zvovovoCCCCC cke[1:0] z0*0*voCCCCC dq[63:32] zz*z*vbzCCCC dq[31:0] zz*z*vbCCCCC cb[7:0] zz*z*vbCCCCC dqs[8] , dqs#[8] zz*z*vbCCCCC dqs[7:4] , dqs#[7:4] zz*z*vbzCCCC dqs[3:0] , dqs#[3:0] zz*z*vbCCCCC dm[8] zvo*vo*voCCCCC dm[7:4] zvo*vo*voCCCCC dm[3:0] zvo*vo*voCCCCC m_vref CaiaiaiCCCCC odt[1:0] z0*0*voCCCCC m_cal[1:0] zz*z*aoCCCCC a[24:0] zhhvoCCCCC d[15:0] zhhvbCCCCC poe# zhhvoCCCCC pwe# zhhvoCCCCC pb_rstout# z00voCCCCC pce[1:0]# zhhvoCCCCC hs_enum# zzzvoCCCCC hs_lstat CviviviCCCCC hs_led_out z11voCCCCC hs_freq[1:0] / cr_freq[1:0] zhhhCCCCC notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled. h = pulled up to v cc pd = pull-up disabled l = pulled down to v ss odt = on die termination gnd = tie to ground. ea = external arbiter mode ia = internal arbiter mode z = output, pull-up/down disabled vb = acts like a valid bidirectional pin vo = a valid output level is driven. vi = need to drive a valid input level. ao = analog output level ai = analog input level * = after power fail sequence completes - = unaffected by this mode a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin is nc.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 37 package informationintel ? 81348 p_ad[63:32] zzzvbChhCh p_ad[31:0] zz0vbCCCCh p_cbe[7:4]# zzzvbChhCh p_cbe[3:0]# zz0vbCCCCh p_par64 zzzvbChhCh p_req64# zvi0vbC C h C h p_ack64# zzzvbCChCh p_par zz0vbCCCCh p_frame# zvivovbCChCh p_irdy# zvivovbCChCh p_trdy# zvivovbCChCh p_stop# zvivovbCChCh p_devsel# zvivovbCChCh p_serr# zzzvbCChCh p_rstout# z00voCCCCvo p_perr# zvivovbCChCh p_m66en CviviviCCCCh p_idsel CviviviCCCCh p_gnt[0]# / p_req# z z (ea) h (ia) z (ea) h (ia) voCCCCh p_req[0]# / p_gnt# C vi (ea) vi (ea) h (ia) vi (ea) h (ia) CCCCh p_gnt[3:1]# zhhvoCCCCh p_req[3:1]# ChhhCCCCh p_clkin CviviviCCCCgnd p_clkout zzvovoCCCCz p_clko[3:0] zzvovoCCCCz p_pcixcap CaiaiaiCCCCgnd p_bmi zvovovoCCCCvo p_cal[2:0] zaoaoaoCCCCvo s_clkp0 , s_clkn0 CviviviCCCCC s_txp[7:0] , s_txn[7:0] C11voCCCCC s_rxp[7:0] , s_rxn[7:0] CididviCCCCC table 14. functional pin mode behavior (sheet 2 of 4) pin b o u n d a r y s c a n h i g h z r e s e t ( e n d p o i n t ) r e s e t ( c e n t r a l r e s o u r c e ) n o r m a l 3 2 - b i t s d r a m p c i x _ 3 2 b i t # p c i x _ p u l l u p # w h e n o n l y p c i - x i n t e r f a c e a c t i v e w h e n o n l y p c i e x p r e s s * i n t e r f a c e a c t i v e notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled. h = pulled up to v cc pd = pull-up disabled l = pulled down to v ss odt = on die termination gnd = tie to ground. ea = external arbiter mode ia = internal arbiter mode z = output, pull-up/down disabled vb = acts like a valid bidirectional pin vo = a valid output level is driven. vi = need to drive a valid input level. ao = analog output level ai = analog input level * = after power fail sequence completes - = unaffected by this mode a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin is nc.
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 38 order number: 315038-003us rbias[1:0] CaoaoaoCCCCC rbias_sense[1:0] CaiaiaiCCCCC s_act0 / sclock0 zzzvoCCCCC s_stat0 / sload0 zzzvoCCCCC s_act1 zzzvoCCCCC s_stat1 zzzvoCCCCC s_act2 / sdatain0 zzzvoCCCCC s_stat2 / sdataout0 zzzvoCCCCC s_act3 zzzvoCCCCC s_stat3 zzzvoCCCCC s_act4 / sclock1 zzzvoCCCCC s_stat4 / sload1 zzzvoCCCCC s_act5 zzzvoCCCCC s_stat5 zzzvoCCCCC s_act6 / sdatain1 zzzvoCCCCC s_stat6 / sdataout1 zzzvoCCCCC s_act7 zzzvoCCCCC s_stat7 zzzvoCCCCC refclkp , refclkn C vivivi C C C gnd/ vi C petp[7:0] , petn[7:0] CzzvoCCCzC perp[7:0] , pern[7:0] CididviCCCzC pe_calp CaoaoaoCCCzC pe_caln CaoaoaoCCCzC p_int[d:a]# / xint[3:0]# z z/vi z/vi vb C C h C C xint[7:4]# CviviviCCCCC gpio[7:0] / xint[15:8]# / pmonout zvivivbCCCCC hpi# CviviviCCCCC nmi0# CviviviCCCCC nmi1# CviviviCCCCC scl0 zzzvbCCCCC table 14. functional pin mode behavior (sheet 3 of 4) pin b o u n d a r y s c a n h i g h z r e s e t ( e n d p o i n t ) r e s e t ( c e n t r a l r e s o u r c e ) n o r m a l 3 2 - b i t s d r a m p c i x _ 3 2 b i t # p c i x _ p u l l u p # w h e n o n l y p c i - x i n t e r f a c e a c t i v e w h e n o n l y p c i e x p r e s s * i n t e r f a c e a c t i v e notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled. h = pulled up to v cc pd = pull-up disabled l = pulled down to v ss odt = on die termination gnd = tie to ground. ea = external arbiter mode ia = internal arbiter mode z = output, pull-up/down disabled vb = acts like a valid bidirectional pin vo = a valid output level is driven. vi = need to drive a valid input level. ao = analog output level ai = analog input level * = after power fail sequence completes - = unaffected by this mode a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin is nc.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 39 package informationintel ? 81348 sda0 zzzvbCCCCC scl1 zzzvbCCCCC sda1 zzzvbCCCCC scl2 zzzvbCCCCC sda2 zzzvbCCCCC smbclk zzzvbCCCCC smbdat zzzvbCCCCC u0_rxd CviviviCCCCC u0_txd z11voCCCCC u0_cts# CviviviCCCCC u0_rts# z11voCCCCC u1_rxd CviviviCCCCC u1_txd z11voCCCCC u1_cts# CviviviCCCCC u1_rts# z11voCCCCC tck CviviviCCCCC tdi ChhhCCCCC tdo CzzvoCCCCC trst# ChhhCCCCC tms ChhhCCCCC p_rst# CviviviCCCCC warm_rst# CviviviCCCCC nc -/zz/hz/hz/hCCCCC thermda CaiaiaiCCCCC thermdc CaoaoaoCCCCC table 14. functional pin mode behavior (sheet 4 of 4) pin b o u n d a r y s c a n h i g h z r e s e t ( e n d p o i n t ) r e s e t ( c e n t r a l r e s o u r c e ) n o r m a l 3 2 - b i t s d r a m p c i x _ 3 2 b i t # p c i x _ p u l l u p # w h e n o n l y p c i - x i n t e r f a c e a c t i v e w h e n o n l y p c i e x p r e s s * i n t e r f a c e a c t i v e notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled. h = pulled up to v cc pd = pull-up disabled l = pulled down to v ss odt = on die termination gnd = tie to ground. ea = external arbiter mode ia = internal arbiter mode z = output, pull-up/down disabled vb = acts like a valid bidirectional pin vo = a valid output level is driven. vi = need to drive a valid input level. ao = analog output level ai = analog input level * = after power fail sequence completes - = unaffected by this mode a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin is nc.
intel ? 81348package information intel ? 81348 i/o processor datasheet december 2007 40 order number: 315038-003us figure 2. 1357-lead fcbga package (top and bottom views)
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 41 datasheetintel ? 81348 the following figures show the intel ? 81348 ballout diagrams: ? figure 3, intel ? 81348 i/o processor balloutpackage top (left side) on page 42 ? figure 4, intel ? 81348 i/o processor balloutpackage top (right side) on page 43 ? figure 5, intel ? 81348 i/o processor balloutpackage bottom (left side) on page 44 ? figure 6, intel ? 81348 i/o processor balloutpackage bottom (right side) on page 45 the following tables show the intel ? 81348 ball and signal listings: ? table 15, intel ? 81348 i/o processor 1357-lead packagealphabetical ball listings on page 46 ? table 16, intel ? 81348 i/o processor 1357-lead packagealphabetical signal listings on page 54
intel ? 81348datasheet intel ? 81348 i/o processor datasheet december 2007 42 order number: 315038-003us figure 3. intel ? 81348 i/o processor balloutpackage top (left side) abcdefghjklmnprtuvw 37 vss dq [63] dqs [7] dqs# [7] dq [57] dq [56] dq [60] dq [43] dq [47] dqs [5] dqs# [5] dq [41] dq [40] dq [44] cb [2] cb [6] dqs# [8] 36 vss dq [59] dq [58] dq [62] vss dm [7] dq [61] vss vss dq [42] dq [46] vss dm [5] dq [45] vss cb [3] cb [7] dqs [8] 35 vss nc dq [51] dq [50] dqs [6] dqs# [6] dm [6] dq [53] dq [52] dq [35] dq [34] dqs [4] dqs# [4] dm [4] dq [37] dq [36] m_ck# [2] vss dm [8] 34 nc nc vss dq [55] dq [54] vss dq[ 49] dq [48] vss vss dq [39] dq [38] vss dq [33] dq [32] vss m_ck [2] m_ck# [0] m_ck [0] 33 nc nc ma[14] a nc vss odt [1] cs# [1] ma [13] odt [0] cas# we# vss cs# [0] ras# ba [0] ma [10] ba [1] ma [0] vss 32 nc nc nc nc nc vcc3 p3 vcc3 p3 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 31 nc nc nc nc nc nc vcc3 p3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 30 nc vss nc vss nc nc vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 29 nc nc nc nc nc nc vcc3 p3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vsspllx therm da nc 28 nc nc nc nc nc nc vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x therm dc vcc1 p2x 27 s_ act1 vss s_ stat5 vss s_ act4 s_ stat3 vcc3 p3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 26 s_ act5 s_ stat2 s_ act0 s_ stat7 s_ stat6 s_ stat4 vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 25 s_ stat0 s_ act2 s_ act3 s_ act7 s_ stat1 s_ act6 vcc3 p3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 24 vssas vssas vssas vssas vcc1 p2as vcc1 p2as vcc1 p2as vss vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 23 s_ rxp[3] s_ rxn[3] s_ txp[3] s_ txn [3] vcc1 p2as vcc1 p2as vcc1 p2as vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 22 s_ rxp[1] s_ rxn[1] s_ txp[1] s_ txn [1] vcc1 p2as vcc1 p2as vcc1 p2as vss vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 21 vssas vssas vssas vssas rbias_ sense [0] nc nc s_ clkp0 vssplls0 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 20 s_ rxp[0] s_ rxn[0] s_ txp[0] s_ txn [0] rbias [0] nc nc s_ clkn0 vcc1 p2plls0 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 19 s_ rxp[2] s_ rxn[2] s_ txp[2] s_ txn [2] vcc1 p8s vcc1 p8s vcc1 p8s vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 18 vssas vssas vssas vssas vcc1 p8s vcc1 p8s vcc1 p8s vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 17 s_ rxp[7] s_ rxn[7] s_ txp[7] s_ txn [7] vcc1 p2ds vssds vssds vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 16 s_ rxp[5] s_ rxn[5] s_ txp[5] s_ txn [5] rbias_ sense [1] nc nc vss vssplls1 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 15 vssas vssas vssas vssas rbias [1] nc nc vss vcc1 p2plls1 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 14 s_ rxp[4] s_ rxn[4] s_ txp[4] s_ txn [4] vssds vcc1 p2ds vssds vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 13 s_ rxp[6] s_ rxn[6] s_ txp[6] s_ txn [6] vcc1 p2ds vssds vcc1 p2ds vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 12 vssas vssas vssas vssas vssds vcc1 p2ds vcc1 p2ds vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 11 gpio [1] gpio [3] gpio [7] gpio [5] gpio [6] vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vsspllp vcc1 p2pllp vss vcc1 p2 vss vcc1 p2 vss 10 gpio [0] vss gpio [2] vss gpio [4] vcc3 p3 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 9 xint# [1] xint# [3] xint# [5] xint# [4] xint# [7] vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 8 xint# [2] xint# [0] xint# [6] nmi0# hs_ led_out vcc3 p3 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 7 hs_ enum# vss hpi# vss nmi1# vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 6 u0_ rts# u0_ rx d hs_ lstat hs_ freq [1] hs_ freq [0] vcc3 p3 vcc3 p3 vccvio vcc3 p3 vcc3 p3 vccvio vccvio vcc3 p3 vccvio vcc3 p3 vcc3 p3 vccvio vcc3 p3 vcc3 p3 5 u0_ cts# u0_ tx d u1_ rx d nc vcc3 p3 p_ cal [0] p_ gnt# [3] vccvio p_ gnt# [0] p_ ad [31] vccvio p_ ad [26] p_ idsel vccvio p_ ad [16] p_ trdy# vccvio p_ ad [13] p_ ad [9] 4 u1_ cts# u1_ tx d u1_ rts# vss warm_rs t# p_ bmi vss p_ req# [3] p_ gnt# [1] vss p_ ad [30] p_ ad [24] vss p_ ad [20] p_ frame# vss p_ par p_ ad [11] vss 3vss p_ clko [3] p_ clko [2] p_ cal [2] nc p_ cal [1] p_ req# [2] p_ gnt# [2] nc p_ ad [27] p_ ad [28] p_ ad [23] p_ ad [22] p_ ad [18] p_ devsel# p_ stop# p_ ad [15] p_ ad [12] p_ cbe# [0] 2 vss p_ clko [0] p_ clkout vss p_ rst# vssnc ncvss p_ ad [25] p_ ad [21] vss p_ cbe# [2] p_ pcixcap vss p_ cbe# [1] p_ ad [10] vss 1 vss p_ clkin p_ clko [1] p_ rstout# nc p_ req# [1] p_ req# [0] p_ ad [29] p_ cbe# [3] p_ ad [19] p_ ad [17] p_ irdy# p_ perr# p_ serr# p_ ad [14] p_ m66en vss a. ma[14] only needed for 4gb memory support, otherwise this pin is nc.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 43 datasheetintel ? 81348 figure 4. intel ? 81348 i/o processor balloutpackage top (right side) y aaabacadaeafagahaj akalamanaparatau cb [1] cb [0] dq [27] dq [31] dqs [3] dqs# [3] dq [25] dq [24] dq [28] dq [11] dq [15] dqs [1] dqs# [1] dq [9] dm [1] vss 37 cb [5] cb [4] vss dq [26] dq [30] vss dm [3] dq [29] vss vss dq [10] dq [14] vss dq [8] dq [13] dq [12] vss 36 vss m_ck [1] dq [19] dq [18] dqs [2] dqs# [2] dm [2] dq [21] dq [20] dq [3] dq [2] dqs [0] dqs# [0] dm [0] dq [5] dq [4] m_ cal [0] vss 35 ma [2] m_ck# [1] vss dq [23] dq [22] vss dq [17] dq [16] vss vss dq [7] dq [6] vss dq [1] dq [0] vss m_ cal [1] vss 34 ma [1] ma [3] ma [4] ma [6] vss ma [5] ma [8] ma [7] ma [9] ma [11] ma [12] vss ba [2] cke [0] cke [1] m_ rst# m_ vref vss 33 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 32 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 vcc3 p3 vss tck vss trst# 31 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 vcc3 p3 vcc3 p3 tdo tms tdi 30 vcc3 p3pllx vss vcc1 p2x vssplld vcc1 p2plld vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 scl1 sda2 sda1 scl0 smbclk 29 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 scl2 vss sda0 vss smbdat 28 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x 27 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e 26 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p8e vcc1 p8e vsse vsse vsse vsse 25 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc1 p2ae vcc1 p8e petn [7] petp [7] pern [7] perp [7] 24 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vss vcc1 p2ae vcc1 p8e petn [6] petp [6] pern [6] perp [6] 23 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vss vcc1 p2 vcc1 p2ae vcc1 p8e vsse vsse vsse vsse 22 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2ae vcc1 p8e petn [5] petp [5] pern [5] perp [5] 21 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 refclkp nc nc pe_cal p petn [4] petp [4] pern [4] perp [4] 20 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss refclkn nc nc pe_cal n vsse vsse vsse vsse 19 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2ae vcc1 p8e petn [3] petp [3] pern [3] perp [3] 18 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2ae vcc1 p8e petn [2] petp [2] pern [2] perp [2] 17 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2ae vcc1 p2e vsse vsse vsse vsse 16 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2ae vcc1 p2e petn [1] petp [1] pern [1] perp [1] 15 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2e vcc1 p2e petn [0] petp [0] pern [0] perp [0] 14 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2e vcc1 p2e vsse vsse vsse vsse 13 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 12 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 pce# [1] a [21] a [19] a [18] a [22] 11 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc3 p3 a [20] vss pce# [0] vss a [13] 10 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 nc a [9] a [12] a [8] a [14] 9 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc3 p3 pur1 a [10] pb_rsto ut# a [1] a [6] 8 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 a [11] vss a [15] vss a [2] 7 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vcc3 p3 d [15] a [16] a [17] a [3] a [7] 6 p_ ad [4] vccvio p_ cbe# [7] p_ par64 vccvio p_ ad [56] p_ ad [52] vccvio p_ ad [44] p_ ad [40] vccvio p_ ad [32] d [10] vcc3 p3 d [9] d [4] a [4] a [5] 5 p_ ad [6] p_ ad [0] vss p_ cbe# [5] p_ ad [60] vss p_ ad [54] p_ ad [48] vss p_ ad [42] p_ ad [36] vss poe# d [2] vss d [3] d [8] d [1] 4 p_ ad [5] p_ ad [2] p_ req64# p_ ad [63] p_ ad [62] p_ ad [58] p_ ad [51] p_ ad [50] p_ ad [46] p_ ad [39] p_ ad [38] p_ ad [34] pwe# d [12] d [11] a [23] d [0] vss 3 p_ ad [7] p_ ad [1] vss p_ cbe# [4] p_ ad [59] vss p_ ad [53] p_ ad [47] vss p_ ad [41] p_ ad [35] vss d [14] d [6] d [5] a [0] vss 2 p_ ad [8] p_ ad [3] p_ ack64# p_ cbe# [6] p_ ad [61] p_ ad [57] p_ ad [55] p_ ad [49] p_ ad [45] p_ ad [43] p_ ad [37] p_ ad [33] a [24] d [7] d [13] vss 1
intel ? 81348datasheet intel ? 81348 i/o processor datasheet december 2007 44 order number: 315038-003us figure 5. intel ? 81348 i/o processor balloutpackage bottom (left side) au at ar ap an am al ak aj ah ag af ae ad ac ab aa y w 37 vss dm [1] dq [9] dqs# [1] dqs [1] dq [15] dq [11] dq [28] dq [24] dq [25] dqs# [3] dqs [3] dq [31] dq [27] cb [0] cb [1] dqs# [8] 36 vss dq [12] dq [13] dq [8] vss dq [14] dq [10] vss vss dq [29] dm [3] vss dq [30] dq [26] vss cb [4] cb [5] dqs [8] 35 vss m_ cal [0] dq [4] dq [5] dm [0] dqs# [0] dqs [0] dq [2] dq [3] dq [20] dq [21] dm [2] dqs# [2] dqs [2] dq [18] dq [19] m_ck [1] vss dm [8] 34 vss m_ cal [1] vss dq [0] dq [1] vss dq [6] dq [7] vss vss dq [16] dq [17] vss dq [22] dq [23] vss m_ck# [1] ma [2] m_ck [0] 33 vss m_ vref m_ rst# cke [1] cke [0] ba [2] vss ma [12] ma [11] ma [9] ma [7] ma [8] ma [5] vss ma [6] ma [4] ma [3] ma [1] vss 32 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 31 trst# vss tck vss vcc3 p3 vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 30 tdi tms tdo vcc3 p3 vcc3 p3 vcc3 p3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 29 smbclk scl0 sda1 sda2 scl1 vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2plld vssplld vcc1 p2x vss vcc3 p3pllx nc 28 smbdat vss sda0 vss scl2 vcc3 p3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 27 vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 26 vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 25 vsse vsse vsse vsse vcc1 p8e vcc1 p8e vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 24 perp [7] pern [7] petp [7] petn [7] vcc1 p8e vcc1 p2ae vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 23 perp [6] pern [6] petp [6] petn [6] vcc1 p8e vcc1 p2ae vss vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 22 vsse vsse vsse vsse vcc1 p8e vcc1 p2ae vcc1 p2 vss vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 21 perp [5] pern [5] petp [5] petn [5] vcc1 p8e vcc1 p2ae vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 20 perp [4] pern [4] petp [4] petn [4] pe_cal p nc nc refclkp vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 19 vsse vsse vsse vsse pe_cal n nc nc refclkn vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 18 perp [3] pern [3] petp [3] petn [3] vcc1 p8e vcc1 p2ae vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 17 perp [2] pern [2] petp [2] petn [2] vcc1 p8e vcc1 p2ae vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 16 vsse vsse vsse vsse vcc1 p2e vcc1 p2ae vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 15 perp [1] pern [1] petp [1] petn [1] vcc1 p2e vcc1 p2ae vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 14 perp [0] pern [0] petp [0] petn [0] vcc1 p2e vcc1 p2e vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 13 vsse vsse vsse vsse vcc1 p2e vcc1 p2e vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 12 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 11 a [22] a [18] a [19] a [21] pce# [1] vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 10 a [13] vss pce# [0] vss a [20] vcc3 p3 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 9 a [14] a [8] a [12] a [9] nc vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 8 a [6] a [1] pb_rst out# a [10] pur1 vcc3 p3 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 7 a [2] vss a [15] vss a [11] vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 6 a [7] a [3] a [17] a [16] d [15] vcc3 p3 vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 5 a [5] a [4] d [4] d [9] vcc3 p3 d [10] p_ ad [32] vccvio p_ ad [40] p_ ad [44] vccvio p_ ad [52] p_ ad [56] vccvio p_ par64 p_ cbe# [7] vccvio p_ ad [4] p_ ad [9] 4 d [1] d [8] d [3] vss d [2] poe# vss p_ ad [36] p_ ad [42] vss p_ ad [48] p_ ad [54] vss p_ ad [60] p_ cbe# [5] vss p_ ad [0] p_ ad [6] vss 3vss d [0] a [23] d [11] d [12] pwe# p_ ad [34] p_ ad [38] p_ ad [39] p_ ad [46] p_ ad [50] p_ ad [51] p_ ad [58] p_ ad [62] p_ ad [63] p_ req64# p_ ad [2] p_ ad [5] p_ cbe# [0] 2 vss a [0] d [5] d [6] d [14] vss p_ ad [35] p_ ad [41] vss p_ ad [47] p_ ad [53] vss p_ ad [59] p_ cbe# [4] vss p_ ad [1] p_ ad [7] vss 1 vss d [13] d [7] a [24] p_ ad [33] p_ ad [37] p_ ad [43] p_ ad [45] p_ ad [49] p_ ad [55] p_ ad [57] p_ ad [61] p_ cbe# [6] p_ ack64# p_ ad [3] p_ ad [8] vss
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 45 datasheetintel ? 81348 figure 6. intel ? 81348 i/o processor balloutpackage bottom (right side) vutrpnml k jhgfedcba cb [6] cb [2] dq [44] dq [40] dq [41] dqs# [5] dqs [5] dq [47] dq [43] dq [60] dq [56] dq [57] dqs# [7] dqs [7] dq [63] vss 37 cb [7] cb [3] vss dq [45] dm [5] vss dq [46] dq [42] vss vss dq [61] dm [7] vss dq [62] dq [58] dq [59] vss 36 vss m_ck# [2] dq [36] dq [37] dm [4] dqs# [4] dqs [4] dq [34] dq [35] dq [52] dq [53] dm [6] dqs# [6] dqs [6] dq [50] dq [51] nc vss 35 m_ck# [0] m_ck [2] vss dq [32] dq [33] vss dq [38] dq [39] vss vss dq [48] dq [49] vss dq [54] dq [55] vssncnc34 ma [0] ba [1] ma [10] ba [0] ras# cs# [0] vss we# cas# odt [0] ma [13] cs# [1] odt [1] vss nc ma [14] a nc nc 33 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc1 p8 vcc3 p3 vcc3 p3 nc nc nc nc nc 32 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 nc nc nc nc nc nc 31 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 nc nc vss nc vss nc 30 therm da vsspllx vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 nc nc nc nc nc nc 29 therm dc vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 nc nc nc nc nc nc 28 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 s_ stat3 s_ act4 vss s_ stat5 vss s_ act1 27 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 s_ stat4 s_ stat6 s_ stat7 s_ act0 s_ stat2 s_ act5 26 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 s_ act6 s_ stat1 s_ act7 s_ act3 s_ act2 s_ stat0 25 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vss vcc1 p2as vcc1 p2as vcc1 p2as vssas vssas vssas vssas 24 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vcc1 p2as vcc1 p2as vcc1 p2as s_ txn [3] s_ txp[3] s_ rxn[3] s_ rxp[3] 23 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vss vcc1 p2as vcc1 p2as vcc1 p2as s_ txn [1] s_ txp[1] s_ rxn[1] s_ rxp[1] 22 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vssplls 0 s_ clkp nc nc rbias_ sense [0] vssas vssas vssas vssas 21 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2plls0 s_ clkn nc nc rbias [0] s_ txn [0] s_ txp[0] s_ rxn[0] s_ rxp[0] 20 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p8s vcc1 p8s vcc1 p8s s_ txn [2] s_ txp[2] s_ rxn[2] s_ rxp[2] 19 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p8s vcc1 p8s vcc1 p8s vssas vssas vssas vssas 18 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vssds vssds vcc1 p2ds s_ txn [7] s_ txp[7] s_ rxn[7] s_ rxp[7] 17 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vssplls 1 vss nc nc rbias_ sense [1] s_ txn [5] s_ txp[5] s_ rxn[5] s_ rxp[5] 16 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2plls1 vss nc nc rbias [1] vssas vssas vssas vssas 15 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vssds vcc1 p2ds vssds s_ txn [4] s_ txp[4] s_ rxn[4] s_ rxp[4] 14 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc1 p2ds vssds vcc1 p2ds s_ txn [6] s_ txp[6] s_ rxn[6] s_ rxp[6] 13 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2ds vcc1 p2ds vssds vssas vssas vssas vssas 12 vcc1 p2 vss vcc1 p2 vss vcc1 p2pllp vsspllp vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 gpio [6] gpio [5] gpio [7] gpio [3] gpio [1] 11 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc3 p3 gpio [4] vss gpio [2] vss gpio [0] 10 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 xint# [7] xint# [4] xint# [5] xint# [3] xint# [1] 9 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vcc3 p3 hs_ led_out nmi0# xint# [6] xint# [0] xint# [2] 8 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 nmi1# vss hpi# vss hs_ enum# 7 vcc3 p3 vccvio vcc3 p3 vcc3 p3 vccvio vcc3 p3 vccvio vccvio vcc3 p3 vcc3 p3 vccvio vcc3 p3 vcc3 p3 hs_ freq [0] hs_ freq [1] hs_ lstat u0_ rx d u0_ rts# 6 p_ ad [13] vccvio p_ trdy# p_ ad [16] vccvio p_ idsel p_ ad [26] vccvio p_ ad [31] p_ gnt# [0] vccvio p_ gnt# [3] p_ cal [0] vcc3 p3 nc u1_ rx d u0_ tx d u0_ cts# 5 p_ ad [11] p_ par vss p_ frame# p_ ad [20] vss p_ ad [24] p_ ad [30] vss p_ gnt# [1] p_ req# [3] vss p_ bmi warm_ rst# vss u1_ rts# u1_ tx d u1_ cts# 4 p_ ad [12] p_ ad [15] p_ stop# p_ devsel # p_ ad [18] p_ ad [22] p_ ad [23] p_ ad [28] p_ ad [27] nc p_ gnt# [2] p_ req# [2] p_ cal [1] nc p_ cal [2] p_ clko [2] p_ clko [3] vss 3 p_ ad [10] p_ cbe# [1] vss p_ pcixca p p_ cbe# [2] vss p_ ad [21] p_ ad [25] vss nc nc vss p_ rst# vss p_ clkout p_ clko [0] vss 2 p_ m66en p_ ad [14] p_ serr# p_ perr# p_ irdy# p_ ad [17] p_ ad [19] p_ cbe# [3] p_ ad [29] p_ req# [0] p_ req# [1] nc p_ rstout# p_ clko [1] p_ clkin vss 1 a. ma[14] is only needed for 4gb memory support, otherwise this pin remains nc.
intel ? 81348datasheet intel ? 81348 i/o processor datasheet december 2007 46 order number: 315038-003us table 15. intel ? 81348 i/o processor 1357-lead packagealphabetical ball listings (sheet 1 of 8) ball signal ball signal ball signal ball signal ball signal a1 C b1 C c1 vss d1 p_clkin e1 p_clko[1] a2 C b2 vss c2 p_clko[0] d2 p_clkout e2 vss a3 vss b3 p_clko[3] c3 p_clko[2] d3 p_cal[2] e3 nc a4 u1_cts# b4 u1_txd c4 u1_rts# d4 vss e4 warm_rst# a5 u0_cts# b5 u0_txd c5 u1_rxd d5 nc e5 vcc3p3 a6 u0_rts# b6 u0_rxd c6 hs_lstat d6 hs_freq[1] e6 hs_freq[0] a7 hs_enum# b7 vss c7 hpi# d7 vss e7 nmi1# a8 xint#[2] b8 xint#[0] c8 xint#[6] d8 nmi0# e8 hs_led_out a9 xint#[1] b9 xint#[3] c9 xint#[5] d9 xint#[4] e9 xint#[7] a10 gpio[0] b10 vss c10 gpio[2] d10 vss e10 gpio[4] a11 gpio[1] b11 gpio[3] c11 gpio[7] d11 gpio[5] e11 gpio[6] a12 vssas b12 vssas c12 vssas d12 vssas e12 vssds a13 s_rxp[6] b13 s_rxn[6] c13 s_txp[6] d13 s_txn[6] e13 vcc1p2ds a14 s_rxp[4] b14 s_rxn[4] c14 s_txp[4] d14 s_txn[4] e14 vssds a15 vssas b15 vssas c15 vssas d15 vssas e15 rbias[1] a16 s_rxp[5] b16 s_rxn[5] c16 s_txp[5] d16 s_txn[5] e16 rbias_sense[1] a17 s_rxp[7] b17 s_rxn[7] c17 s_txp[7] d17 s_txn[7] e17 vcc1p2ds a18 vssas b18 vssas c18 vssas d18 vssas e18 vcc1p8s a19 s_rxp[2] b19 s_rxn[2] c19 s_txp[2] d19 s_txn[2] e19 vcc1p8s a20 s_rxp[0] b20 s_rxn[0] c20 s_txp[0] d20 s_txn[0] e20 rbias[0] a21 vssas b21 vssas c21 vssas d21 vssas e21 rbias_sense[0] a22 s_rxp[1] b22 s_rxn[1] c22 s_txp[1] d22 s_txn[1] e22 vcc1p2as a23 s_rxp[3] b23 s_rxn[3] c23 s_txp[3] d23 s_txn[3] e23 vcc1p2as a24 vssas b24 vssas c24 vssas d24 vssas e24 vcc1p2as a25 s_stat0 b25 s_act2 c25 s_act3 d25 s_act7 e25 s_stat1 a26 s_act5 b26 s_stat2 c26 s_act0 d26 s_stat7 e26 s_stat6 a27 s_act1 b27 vss c27 s_stat5 d27 vss e27 s_act4 a28 nc b28 nc c28 nc d28 nc e28 nc a29 nc b29 nc c29 nc d29 nc e29 nc a30 nc b30 vss c30 nc d30 vss e30 nc a31 nc b31 nc c31 nc d31 nc e31 nc a32 nc b32 nc c32 nc d32 nc e32 nc a33 nc b33 nc c33 ma[14] a d33 nc e33 vss a34 nc b34 nc c34 vss d34 dq[55] e34 dq[54] a35 vss b35 nc c35 dq[51] d35 dq[50] e35 dqs[6] a36 C b36 vss c36 dq[59] d36 dq[58] e36 dq[62] a37 C b37 C c37 vss d37 dq[63] e37 dqs[7]
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 47 datasheetintel ? 81348 f1 p_rstout# g2 vss h3 p_gnt#[2] j4 p_gnt#[1] k5 p_ad[31] f2 p_rst# g3 p_req#[2] h4 p_req#[3] j5 p_gnt#[0] k6 vcc3p3 f3 p_cal[1] g4 vss h5 vccvio j6 vcc3p3 k7 vcc1p2 f4 p_bmi g5 p_gnt#[3] h6 vccvio j7 vss k8 vss f5 p_cal[0] g6 vcc3p3 h7 vcc1p2 j8 vcc1p2 k9 vcc1p2 f6 vcc3p3 g7 vss h8 vss j9 vss k10 vss f7 vcc3p3 g8 vcc1p2 h9 vcc1p2 j10 vcc1p2 k11 vcc1p2 f8 vcc3p3 g9 vss h10 vss j11 vss k12 vss f9 vcc3p3 g10 vcc1p2 h11 vcc1p2 j12 vcc1p2 k13 vcc1p2 f10 vcc3p3 g11 vss h12 vss j13 vss k14 vss f11 vcc3p3 g12 vcc1p2ds h13 vcc1p2 j14 vcc1p2 k15 vcc1p2 f12 vcc1p2ds g13 vcc1p2ds h14 vss j15 vcc1p2plls1 k16 vss f13 vssds g14 vssds h15 vss j16 vssplls1 k17 vcc1p2 f14 vcc1p2ds g15 nc h16 vss j17 vss k18 vss f15 nc g16 nc h17 vcc1p2 j18 vcc1p2 k19 vcc1p2 f16 nc g17 vssds h18 vss j19 vss k20 vss f17 vssds g18 vcc1p8s h19 vcc1p2 j20 vcc1p2plls0 k21 vcc1p2 f18 vcc1p8s g19 vcc1p8s h20 s_clkn0 j21 vssplls0 k22 vss f19 vcc1p8s g20 nc h21 s_clkp0 j22 vcc1p2 k23 vcc1p2x f20 nc g21 nc h22 vss j23 vss k24 vss f21 nc g22 vcc1p2as h23 vcc1p2 j24 vcc1p2 k25 vcc1p2x f22 vcc1p2as g23 vcc1p2as h24 vss j25 vss k26 vss f23 vcc1p2as g24 vcc1p2as h25 vcc1p2x j26 vcc1p2x k27 vcc1p2x f24 vcc1p2as g25 vcc3p3 h26 vss j27 vss k28 vss f25 s_act6 g26 vcc3p3 h27 vcc1p2x j28 vcc1p2x k29 vcc1p2x f26 s_stat4 g27 vcc3p3 h28 vss j29 vss k30 vss f27 s_stat3 g28 vcc3p3 h29 vcc1p2x j30 vcc1p2x k31 vcc1p2x f28 nc g29 vcc3p3 h30 vss j31 vss k32 vcc1p8 f29 nc g30 vcc3p3 h31 vcc1p2x j32 vcc1p8 k33 cas# f30 nc g31 vcc3p3 h32 vcc1p8 j33 odt[0] k34 vss f31 nc g32 vcc3p3 h33 ma[13] j34 vss k35 dq[35] f32 vcc3p3 g33 cs#[1] h34 dq[48] j35 dq[52] k36 vss f33 odt[1] g34 dq[49] h35 dq[53] j36 vss k37 dq[43] f34 vss g35 dm[6] h36 dq[61] j37 dq[60] l1 p_cbe#[3] f35 dqs#[6] g36 dm[7] h37 dq[56] k1 p_ad[29] l2 p_ad[25] f36 vss g37 dq[57] j1 p_req#[0] k2 vss l3 p_ad[28] f37 dqs#[7] h1 p_req#[1] j2 nc k3 p_ad[27] l4 p_ad[30] g1 nc h2 nc j3 nc k4 vss l5 vccvio table 15. intel ? 81348 i/o processor 1357-lead packagealphabetical ball listings (sheet 2 of 8) ball signal ball signal ball signal ball signal ball signal
intel ? 81348datasheet intel ? 81348 i/o processor datasheet december 2007 48 order number: 315038-003us l6 vccvio m7 vcc1p2 n8 vcc1p2 p9 vcc1p2 r10 vcc1p2 l7 vss m8 vss n9 vss p10 vss r11 vss l8 vcc1p2 m9 vcc1p2 n10 vcc1p2 p11 vcc1p2pllp r12 vcc1p2 l9 vss m10 vss n11 vsspllp p12 vss r13 vss l10 vcc1p2 m11 vcc1p2 n12 vcc1p2 p13 vcc1p2 r14 vcc1p2 l11 vss m12 vss n13 vss p14 vss r15 vss l12 vcc1p2 m13 vcc1p2 n14 vcc1p2 p15 vcc1p2 r16 vcc1p2 l13 vss m14 vss n15 vss p16 vss r17 vss l14 vcc1p2 m15 vcc1p2 n16 vcc1p2 p17 vcc1p2 r18 vcc1p2 l15 vss m16 vss n17 vss p18 vss r19 vss l16 vcc1p2 m17 vcc1p2 n18 vcc1p2 p19 vcc1p2 r20 vcc1p2 l17 vss m18 vss n19 vss p20 vss r21 vss l18 vcc1p2 m19 vcc1p2 n20 vcc1p2 p21 vcc1p2 r22 vcc1p2x l19 vss m20 vss n21 vss p22 vss r23 vss l20 vcc1p2 m21 vcc1p2 n22 vcc1p2x p23 vcc1p2x r24 vcc1p2x l21 vss m22 vss n23 vss p24 vss r25 vss l22 vcc1p2x m23 vcc1p2x n24 vcc1p2x p25 vcc1p2x r26 vcc1p2x l23 vss m24 vss n25 vss p26 vss r27 vss l24 vcc1p2x m25 vcc1p2x n26 vcc1p2x p27 vcc1p2x r28 vcc1p2x l25 vss m26 vss n27 vss p28 vss r29 vss l26 vcc1p2x m27 vcc1p2x n28 vcc1p2x p29 vcc1p2x r30 vcc1p2x l27 vss m28 vss n29 vss p30 vss r31 vss l28 vcc1p2x m29 vcc1p2x n30 vcc1p2x p31 vcc1p2x r32 vcc1p8 l29 vss m30 vss n31 vss p32 vcc1p8 r33 ba[0] l30 vcc1p2x m31 vcc1p2x n32 vcc1p8 p33 ras# r34 dq[32] l31 vss m32 vcc1p8 n33 cs#[0] p34 dq[33] r35 dq[37] l32 vcc1p8 m33 vss n34 vss p35 dm[4] r36 dq[45] l33 we# m34 dq[38] n35 dqs#[4] p36 dm[5] r37 dq[40] l34 dq[39] m35 dqs[4] n36 vss p37 dq[41] t1 p_serr# l35 dq[34] m36 dq[46] n37 dqs#[5] r1 p_perr# t2 vss l36 dq[42] m37 dqs[5] p1 p_irdy# r2 p_pcixcap t3 p_stop# l37 dq[47] n1 p_ad[17] p2 p_cbe#[2] r3 p_devsel# t4 vss m1 p_ad[19] n2 vss p3 p_ad[18] r4 p_frame# t5 p_trdy# m2 p_ad[21] n3 p_ad[22] p4 p_ad[20] r5 p_ad[16] t6 vcc3p3 m3 p_ad[23] n4 vss p5 vccvio r6 vcc3p3 t7 vcc1p2 m4 p_ad[24] n5 p_idsel p6 vccvio r7 vss t8 vss m5 p_ad[26] n6 vcc3p3 p7 vcc1p2 r8 vcc1p2 t9 vcc1p2 m6 vccvio n7 vss p8 vss r9 vss t10 vss table 15. intel ? 81348 i/o processor 1357-lead packagealphabetical ball listings (sheet 3 of 8) ball signal ball signal ball signal ball signal ball signal
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 49 datasheetintel ? 81348 t11 vcc1p2 u12 vcc1p2 v13 vcc1p2 w14 vcc1p2 y15 vcc1p2 t12 vss u13 vss v14 vss w15 vss y16 vss t13 vcc1p2 u14 vcc1p2 v15 vcc1p2 w16 vcc1p2 y17 vcc1p2 t14 vss u15 vss v16 vss w17 vss y18 vss t15 vcc1p2 u16 vcc1p2 v17 vcc1p2 w18 vcc1p2 y19 vcc1p2 t16 vss u17 vss v18 vss w19 vss y20 vss t17 vcc1p2 u18 vcc1p2 v19 vcc1p2 w20 vcc1p2 y21 vcc1p2 t18 vss u19 vss v20 vss w21 vss y22 vss t19 vcc1p2 u20 vcc1p2 v21 vcc1p2 w22 vcc1p2x y23 vcc1p2x t20 vss u21 vss v22 vss w23 vss y24 vss t21 vcc1p2 u22 vcc1p2x v23 vcc1p2x w24 vcc1p2x y25 vcc1p2x t22 vss u23 vss v24 vss w25 vss y26 vss t23 vcc1p2x u24 vcc1p2x v25 vcc1p2x w26 vcc1p2x y27 vcc1p2x t24 vss u25 vss v26 vss w27 vss y28 vss t25 vcc1p2x u26 vcc1p2x v27 vcc1p2x w28 vcc1p2x y29 vcc3p3pllx t26 vss u27 vss v28 thermdc w29 nc y30 vss t27 vcc1p2x u28 vcc1p2x v29 thermda w30 vcc1p2x y31 vcc1p2x t28 vss u29 vsspllx v30 vss w31 vss y32 vcc1p8 t29 vcc1p2x u30 vcc1p2x v31 vcc1p2x w32 vcc1p8 y33 ma[1] t30 vss u31 vss v32 vcc1p8 w33 vss y34 ma[2] t31 vcc1p2x u32 vcc1p8 v33 ma[0] w34 m_ck[0] y35 vss t32 vcc1p8 u33 ba[1] v34 m_ck#[0] w35 dm[8] y36 cb[5] t33 ma[10] u34 m_ck[2] v35 vss w36 dqs[8] y37 cb[1] t34 vss u35 m_ck#[2] v36 cb[7] w37 dqs#[8] aa1 p_ad[3] t35 dq[36] u36 cb[3] v37 cb[6] y1 p_ad[8] aa2 p_ad[1] t36 vss u37 cb[2] w1 vss y2 p_ad[7] aa3 p_ad[2] t37 dq[44] v1 p_m66en w2 vss y3 p_ad[5] aa4 p_ad[0] u1 p_ad[14] v2 p_ad[10] w3 p_cbe#[0] y4 p_ad[6] aa5 vccvio u2 p_cbe#[1] v3 p_ad[12] w4 vss y5 p_ad[4] aa6 vccvio u3 p_ad[15] v4 p_ad[11] w5 p_ad[9] y6 vccvio aa7 vss u4 p_par v5 p_ad[13] w6 vcc3p3 y7 vcc1p2 aa8 vcc1p2 u5 vccvio v6 vcc3p3 w7 vss y8 vss aa9 vss u6 vccvio v7 vcc1p2 w8 vcc1p2 y9 vcc1p2 aa10 vcc1p2 u7 vss v8 vss w9 vss y10 vss aa11 vss u8 vcc1p2 v9 vcc1p2 w10 vcc1p2 y11 vcc1p2 aa12 vcc1p2 u9 vss v10 vss w11 vss y12 vss aa13 vss u10 vcc1p2 v11 vcc1p2 w12 vcc1p2 y13 vcc1p2 aa14 vcc1p2 u11 vss v12 vss w13 vss y14 vss aa15 vss table 15. intel ? 81348 i/o processor 1357-lead packagealphabetical ball listings (sheet 4 of 8) ball signal ball signal ball signal ball signal ball signal
intel ? 81348datasheet intel ? 81348 i/o processor datasheet december 2007 50 order number: 315038-003us aa16 vcc1p2 ab17 vcc1p2 ac18 vcc1p2 ad19 vcc1p2 ae20 vcc1p2 aa17 vss ab18 vss ac19 vss ad20 vss ae21 vss aa18 vcc1p2 ab19 vcc1p2 ac20 vcc1p2 ad21 vcc1p2 ae22 vcc1p2x aa19 vss ab20 vss ac21 vss ad22 vss ae23 vss aa20 vcc1p2 ab21 vcc1p2 ac22 vcc1p2x ad23 vcc1p2x ae24 vcc1p2x aa21 vss ab22 vss ac23 vss ad24 vss ae25 vss aa22 vcc1p2x ab23 vcc1p2x ac24 vcc1p2x ad25 vcc1p2x ae26 vcc1p2x aa23 vss ab24 vss ac25 vss ad26 vss ae27 vss aa24 vcc1p2x ab25 vcc1p2x ac26 vcc1p2x ad27 vcc1p2x ae28 vcc1p2x aa25 vss ab26 vss ac27 vss ad28 vss ae29 vss aa26 vcc1p2x ab27 vcc1p2x ac28 vcc1p2x ad29 vcc1p2plld ae30 vcc1p2x aa27 vss ab28 vss ac29 vssplld ad30 vss ae31 vss aa28 vcc1p2x ab29 vcc1p2x ac30 vcc1p2x ad31 vcc1p2x ae32 vcc1p8 aa29 vss ab30 vss ac31 vss ad32 vcc1p8 ae33 ma[5] aa30 vcc1p2x ab31 vcc1p2x ac32 vcc1p8 ad33 vss ae34 vss aa31 vss ab32 vcc1p8 ac33 ma[6] ad34 dq[22] ae35 dqs#[2] aa32 vcc1p8 ab33 ma[4] ac34 dq[23] ad35 dqs[2] ae36 vss aa33 ma[3] ab34 vss ac35 dq[18] ad36 dq[30] ae37 dqs#[3] aa34 m_ck#[1] ab35 dq[19] ac36 dq[26] ad37 dqs[3] af1 p_ad[55] aa35 m_ck[1] ab36 vss ac37 dq[31] ae1 p_ad[57] af2 p_ad[53] aa36 cb[4] ab37 dq[27] ad1 p_ad[61] ae2 vss af3 p_ad[51] aa37 cb[0] ac1 p_cbe#[6] ad2 p_ad[59] ae3 p_ad[58] af4 p_ad[54] ab1 p_ack64# ac2 p_cbe#[4] ad3 p_ad[62] ae4 vss af5 p_ad[52] ab2 vss ac3 p_ad[63] ad4 p_ad[60] ae5 p_ad[56] af6 vccvio ab3 p_req64# ac4 p_cbe#[5] ad5 vccvio ae6 vcc3p3 af7 vcc1p2 ab4 vss ac5 p_par64 ad6 vccvio ae7 vss af8 vss ab5 p_cbe#[7] ac6 vccvio ad7 vcc1p2 ae8 vcc1p2 af9 vcc1p2 ab6 vcc3p3 ac7 vss ad8 vss ae9 vss af10 vss ab7 vcc1p2 ac8 vcc1p2 ad9 vcc1p2 ae10 vcc1p2 af11 vcc1p2 ab8 vss ac9 vss ad10 vss ae11 vss af12 vss ab9 vcc1p2 ac10 vcc1p2 ad11 vcc1p2 ae12 vcc1p2 af13 vcc1p2 ab10 vss ac11 vss ad12 vss ae13 vss af14 vss ab11 vcc1p2 ac12 vcc1p2 ad13 vcc1p2 ae14 vcc1p2 af15 vcc1p2 ab12 vss ac13 vss ad14 vss ae15 vss af16 vss ab13 vcc1p2 ac14 vcc1p2 ad15 vcc1p2 ae16 vcc1p2 af17 vcc1p2 ab14 vss ac15 vss ad16 vss ae17 vss af18 vss ab15 vcc1p2 ac16 vcc1p2 ad17 vcc1p2 ae18 vcc1p2 af19 vcc1p2 ab16 vss ac17 vss ad18 vss ae19 vss af20 vss table 15. intel ? 81348 i/o processor 1357-lead packagealphabetical ball listings (sheet 5 of 8) ball signal ball signal ball signal ball signal ball signal
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 51 datasheetintel ? 81348 af21 vcc1p2 ag22 vcc1p2x ah23 vcc1p2x aj24 vcc1p2x ak25 vcc1p2x af22 vss ag23 vss ah24 vss aj25 vss ak26 vss af23 vcc1p2x ag24 vcc1p2x ah25 vcc1p2x aj26 vcc1p2x ak27 vcc1p2x af24 vss ag25 vss ah26 vss aj27 vcc1p2x ak28 vss af25 vcc1p2x ag26 vcc1p2x ah27 vcc1p2x aj28 vcc1p2x ak29 vcc1p2x af26 vss ag27 vss ah28 vss aj29 vss ak30 vss af27 vcc1p2x ag28 vcc1p2x ah29 vcc1p2x aj30 vcc1p2x ak31 vcc1p2x af28 vss ag29 vss ah30 vss aj31 vss ak32 vcc1p8 af29 vcc1p2x ag30 vcc1p2x ah31 vcc1p2x aj32 vcc1p8 ak33 ma[12] af30 vss ag31 vss ah32 vcc1p8 aj33 ma[11] ak34 dq[7] af31 vcc1p2x ag32 vcc1p8 ah33 ma[9] aj34 vss ak35 dq[2] af32 vcc1p8 ag33 ma[7] ah34 vss aj35 dq[3] ak36 dq[10] af33 ma[8] ag34 dq[16] ah35 dq[20] aj36 vss ak37 dq[15] af34 dq[17] ag35 dq[21] ah36 vss aj37 dq[11] al1 p_ad[33] af35 dm[2] ag36 dq[29] ah37 dq[28] ak1 p_ad[37] al2 vss af36 dm[3] ag37 dq[24] aj1 p_ad[43] ak2 p_ad[35] al3 p_ad[34] af37 dq[25] ah1 p_ad[45] aj2 p_ad[41] ak3 p_ad[38] al4 vss ag1 p_ad[49] ah2 vss aj3 p_ad[39] ak4 p_ad[36] al5 p_ad[32] ag2 p_ad[47] ah3 p_ad[46] aj4 p_ad[42] ak5 vccvio al6 vcc3p3 ag3 p_ad[50] ah4 vss aj5 p_ad[40] ak6 vccvio al7 vss ag4 p_ad[48] ah5 p_ad[44] aj6 vccvio ak7 vcc1p2 al8 vcc1p2 ag5 vccvio ah6 vcc3p3 aj7 vss ak8 vss al9 vss ag6 vccvio ah7 vcc1p2 aj8 vcc1p2 ak9 vcc1p2 al10 vcc1p2 ag7 vss ah8 vss aj9 vss ak10 vss al11 vss ag8 vcc1p2 ah9 vcc1p2 aj10 vcc1p2 ak11 vcc1p2 al12 vcc1p2 ag9 vss ah10 vss aj11 vss ak12 vss al13 vss ag10 vcc1p2 ah11 vcc1p2 aj12 vcc1p2 ak13 vcc1p2 al14 vcc1p2 ag11 vss ah12 vss aj13 vss ak14 vss al15 vss ag12 vcc1p2 ah13 vcc1p2 aj14 vcc1p2 ak15 vcc1p2 al16 vcc1p2 ag13 vss ah14 vss aj15 vss ak16 vss al17 vss ag14 vcc1p2 ah15 vcc1p2 aj16 vcc1p2 ak17 vcc1p2 al18 vcc1p2 ag15 vss ah16 vss aj17 vss ak18 vss al19 nc ag16 vcc1p2 ah17 vcc1p2 aj18 vcc1p2 ak19 refclkn al20 nc ag17 vss ah18 vss aj19 vss ak20 refclkp al21 vss ag18 vcc1p2 ah19 vcc1p2 aj20 vcc1p2 ak21 vcc1p2 al22 vcc1p2 ag19 vss ah20 vss aj21 vss ak22 vss al23 vss ag20 vcc1p2 ah21 vcc1p2 aj22 vcc1p2 ak23 vcc1p2 al24 vcc1p2x ag21 vss ah22 vss aj23 vss ak24 vss al25 vss table 15. intel ? 81348 i/o processor 1357-lead packagealphabetical ball listings (sheet 6 of 8) ball signal ball signal ball signal ball signal ball signal
intel ? 81348datasheet intel ? 81348 i/o processor datasheet december 2007 52 order number: 315038-003us al26 vcc1p2x am27 vcc1p2x an28 scl2 ap29 sda2 ar30 tdo al27 vcc1p2x am28 vcc3p3 an29 scl1 ap30 vcc3p3 ar31 tck al28 vcc1p2x am29 vcc3p3 an30 vcc3p3 ap31 vss ar32 vcc1p8 al29 vss am30 vcc3p3 an31 vcc3p3 ap32 vcc1p8 ar33 m_rst# al30 vcc1p2x am31 vcc3p3 an32 vcc1p8 ap33 cke[1] ar34 vss al31 vss am32 vcc1p8 an33 cke[0] ap34 dq[0] ar35 dq[4] al32 vcc1p8 am33 ba[2] an34 dq[1] ap35 dq[5] ar36 dq[12] al33 vss am34 vss an35 dm[0] ap36 dq[13] ar37 vss al34 dq[6] am35 dqs#[0] an36 dq[8] ap37 dm[1] at1 C al35 dqs[0] am36 vss an37 dq[9] ar1 vss at2 vss al36 dq[14] am37 dqs#[1] ap1 d[13] ar2 a[0] at3 d[0] al37 dqs[1] an1 d[7] ap2 d[5] ar3 a[23] at4 d[8] am1 a[24] an2 d[6] ap3 d[11] ar4 d[3] at5 a[4] am2 d[14] an3 d[12] ap4 vss ar5 d[4] at6 a[3] am3 pwe# an4 d[2] ap5 d[9] ar6 a[17] at7 vss am4 poe# an5 vcc3p3 ap6 a[16] ar7 a[15] at8 a[1] am5 d[10] an6 d[15] ap7 vss ar8 pb_rstout# at9 a[8] am6 vcc3p3 an7 a[11] ap8 a[10] ar9 a[12] at10 vss am7 vcc3p3 an8 pur1 ap9 a[9] ar10 pce#[0] at11 a[18] am8 vcc3p3 an9 nc ap10 vss ar11 a[19] at12 vcc1p2 am9 vcc3p3 an10 a[20] ap11 a[21] ar12 vcc1p2 at13 vsse am10 vcc3p3 an11 pce#[1] ap12 vcc1p2 ar13 vsse at14 pern[0] am11 vcc3p3 an12 vcc1p2 ap13 vsse ar14 petp[0] at15 pern[1] am12 vcc1p2 an13 vcc1p2e ap14 petn[0] ar15 petp[1] at16 vsse am13 vcc1p2e an14 vcc1p2e ap15 petn[1] ar16 vsse at17 pern[2] am14 vcc1p2e an15 vcc1p2e ap16 vsse ar17 petp[2] at18 pern[3] am15 vcc1p2ae an16 vcc1p2e ap17 petn[2] ar18 petp[3] at19 vsse am16 vcc1p2ae an17 vcc1p8e ap18 petn[3] ar19 vsse at20 pern[4] am17 vcc1p2ae an18 vcc1p8e ap19 vsse ar20 petp[4] at21 pern[5] am18 vcc1p2ae an19 pe_caln ap20 petn[4] ar21 petp[5] at22 vsse am19 nc an20 pe_calp ap21 petn[5] ar22 vsse at23 pern[6] am20 nc an21 vcc1p8e ap22 vsse ar23 petp[6] at24 pern[7] am21 vcc1p2ae an22 vcc1p8e ap23 petn[6] ar24 petp[7] at25 vsse am22 vcc1p2ae an23 vcc1p8e ap24 petn[7] ar25 vsse at26 vcc1p8e am23 vcc1p2ae an24 vcc1p8e ap25 vsse ar26 vcc1p8e at27 vcc1p2x am24 vcc1p2ae an25 vcc1p8e ap26 vcc1p8e ar27 vcc1p2x at28 vss am25 vcc1p8e an26 vcc1p8e ap27 vcc1p2x ar28 sda0 at29 scl0 am26 vcc1p8e an27 vcc1p2x ap28 vss ar29 sda1 at30 tms table 15. intel ? 81348 i/o processor 1357-lead packagealphabetical ball listings (sheet 7 of 8) ball signal ball signal ball signal ball signal ball signal
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 53 datasheetintel ? 81348 at31 vss au3 vss au12 vcc1p2 au21 perp[5] au30 tdi at32 vcc1p8 au4 d[1] au13 vsse au22 vsse au31 trst# at33 m_vref au5 a[5] au14 perp[0] au23 perp[6] au32 vcc1p8 at34 m_cal[1] au6 a[7] au15 perp[1] au24 perp[7] au33 vss at35 m_cal[0] au7 a[2] au16 vsse au25 vsse au34 vss at36 vss au8 a[6] au17 perp[2] au26 vcc1p8e au35 vss at37 C au9 a[14] au18 perp[3] au27 vcc1p2x au36 C au1 C au10 a[13] au19 vsse au28 smbdat au37 C au2 C au11 a[22] au20 perp[4] au29 smbclk a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin is nc. table 15. intel ? 81348 i/o processor 1357-lead packagealphabetical ball listings (sheet 8 of 8) ball signal ball signal ball signal ball signal ball signal
intel ? 81348datasheet intel ? 81348 i/o processor datasheet december 2007 54 order number: 315038-003us table 16. intel ? 81348 i/o processor 1357-lead packagealphabetical signal listings (sheet 1 of 8) signal ball signal ball signal ball signal ball signal ball C a1 ba[0] r33 dm[5] p36 dq[33] p34 dqs#[6] f35 C a2 ba[1] u33 dm[6] g35 dq[34] l35 dqs#[7] f37 C a36 ba[2] am33 dm[7] g36 dq[35] k35 dqs#[8] w37 C a37 cas# k33 dm[8] w35 dq[36] t35 dqs[0] al35 C b1 cb[0] aa37 dq[0] ap34 dq[37] r35 dqs[1] al37 C b37 cb[1] y37 dq[1] an34 dq[38] m34 dqs[2] ad35 C at1 cb[2] u37 dq[2] ak35 dq[39] l34 dqs[3] ad37 C at37 cb[3] u36 dq[3] aj35 dq[40] r37 dqs[4] m35 C au1 cb[4] aa36 dq[4] ar35 dq[41] p37 dqs[5] m37 C au2 cb[5] y36 dq[5] ap35 dq[42] l36 dqs[6] e35 C au36 cb[6] v37 dq[6] al34 dq[43] k37 dqs[7] e37 C au37 cb[7] v36 dq[7] ak34 dq[44] t37 dqs[8] w36 a[0] ar2 cke[0] an33 dq[8] an36 dq[45] r36 gpio[0] a10 a[1] at8 cke[1] ap33 dq[9] an37 dq[46] m36 gpio[1] a11 a[2] au7 cs#[0] n33 dq[10] ak36 dq[47] l37 gpio[2] c10 a[3] at6 cs#[1] g33 dq[11] aj37 dq[48] h34 gpio[3] b11 a[4] at5 d[0] at3 dq[12] ar36 dq[49] g34 gpio[4] e10 a[5] au5 d[1] au4 dq[13] ap36 dq[50] d35 gpio[5] d11 a[6] au8 d[2] an4 dq[14] al36 dq[51] c35 gpio[6] e11 a[7] au6 d[3] ar4 dq[15] ak37 dq[52] j35 gpio[7] c11 a[8] at9 d[4] ar5 dq[16] ag34 dq[53] h35 hpi# c7 a[9] ap9 d[5] ap2 dq[17] af34 dq[54] e34 hs_enum# a7 a[10] ap8 d[6] an2 dq[18] ac35 dq[55] d34 hs_freq[0] e6 a[11] an7 d[7] an1 dq[19] ab35 dq[56] h37 hs_freq[1] d6 a[12] ar9 d[8] at4 dq[20] ah35 dq[57] g37 hs_led_out e8 a[13] au10 d[9] ap5 dq[21] ag35 dq[58] d36 hs_lstat c6 a[14] au9 d[10] am5 dq[22] ad34 dq[59] c36 m_cal[0] at35 a[15] ar7 d[11] ap3 dq[23] ac34 dq[60] j37 m_cal[1] at34 a[16] ap6 d[12] an3 dq[24] ag37 dq[61] h36 m_ck#[0] v34 a[17] ar6 d[13] ap1 dq[25] af37 dq[62] e36 m_ck#[1] aa34 a[18] at11 d[14] am2 dq[26] ac36 dq[63] d37 m_ck#[2] u35 a[19] ar11 d[15] an6 dq[27] ab37 dqs#[0] am35 m_ck[0] w34 a[20] an10 dm[0] an35 dq[28] ah37 dqs#[1] am37 m_ck[1] aa35 a[21] ap11 dm[1] ap37 dq[29] ag36 dqs#[2] ae35 m_ck[2] u34 a[22] au11 dm[2] af35 dq[30] ad36 dqs#[3] ae37 m_rst# ar33 a[23] ar3 dm[3] af36 dq[31] ac37 dqs#[4] n35 m_vref at33 a[24] am1 dm[4] p35 dq[32] r34 dqs#[5] n37 ma[0] v33
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 55 datasheetintel ? 81348 ma[1] y33 nc d33 p_ad[4] y5 p_ad[42] aj4 p_clko[3] b3 ma[2] y34 nc e3 p_ad[5] y3 p_ad[43] aj1 p_clkout d2 ma[3] aa33 nc e28 p_ad[6] y4 p_ad[44] ah5 p_devsel# r3 ma[4] ab33 nc e29 p_ad[7] y2 p_ad[45] ah1 p_frame# r4 ma[5] ae33 nc e30 p_ad[8] y1 p_ad[46] ah3 p_gnt#[0] j5 ma[6] ac33 nc e31 p_ad[9] w5 p_ad[47] ag2 p_gnt#[1] j4 ma[7] ag33 nc e32 p_ad[10] v2 p_ad[48] ag4 p_gnt#[2] h3 ma[8] af33 nc f15 p_ad[11] v4 p_ad[49] ag1 p_gnt#[3] g5 ma[9] ah33 nc f16 p_ad[12] v3 p_ad[50] ag3 p_idsel n5 ma[10] t33 nc f20 p_ad[13] v5 p_ad[51] af3 p_irdy# p1 ma[11] aj33 nc f21 p_ad[14] u1 p_ad[52] af5 p_m66en v1 ma[12] ak33 nc f28 p_ad[15] u3 p_ad[53] af2 p_par u4 ma[13] h33 nc f29 p_ad[16] r5 p_ad[54] af4 p_par64 ac5 nc a28 nc f30 p_ad[17] n1 p_ad[55] af1 p_pcixcap r2 nc a29 nc f31 p_ad[18] p3 p_ad[56] ae5 p_perr# r1 nc a30 nc g1 p_ad[19] m1 p_ad[57] ae1 p_req#[0] j1 nc a31 nc g15 p_ad[20] p4 p_ad[58] ae3 p_req#[1] h1 nc a32 nc g16 p_ad[21] m2 p_ad[59] ad2 p_req#[2] g3 nc a33 nc g20 p_ad[22] n3 p_ad[60] ad4 p_req#[3] h4 nc a34 nc g21 p_ad[23] m3 p_ad[61] ad1 p_req64# ab3 nc b28 nc h2 p_ad[24] m4 p_ad[62] ad3 p_rst# f2 nc b29 nc j2 p_ad[25] l2 p_ad[63] ac3 p_rstout# f1 nc b31 nc j3 p_ad[26] m5 p_bmi f4 p_serr# t1 nc b32 nc w29 p_ad[27] k3 p_cal[0] f5 p_stop# t3 nc b33 nc al19 p_ad[28] l3 p_cal[1] f3 p_trdy# t5 nc b34 nc al20 p_ad[29] k1 p_cal[2] d3 pb_rstout# ar8 nc b35 nc am19 p_ad[30] l4 p_cbe#[0] w3 pce#[0] ar10 nc c28 nc am20 p_ad[31] k5 p_cbe#[1] u2 pce#[1] an11 nc c29 nc an9 p_ad[32] al5 p_cbe#[2] p2 pe_caln an19 nc c30 nmi0# d8 p_ad[33] al1 p_cbe#[3] l1 pe_calp an20 nc c31 nmi1# e7 p_ad[34] al3 p_cbe#[4] ac2 pern[0] at14 nc c32 odt[0] j33 p_ad[35] ak2 p_cbe#[5] ac4 pern[1] at15 ma[14] a c33 odt[1] f33 p_ad[36] ak4 p_cbe#[6] ac1 pern[2] at17 nc d5 p_ack64# ab1 p_ad[37] ak1 p_cbe#[7] ab5 pern[3] at18 nc d28 p_ad[0] aa4 p_ad[38] ak3 p_clkin d1 pern[4] at20 nc d29 p_ad[1] aa2 p_ad[39] aj3 p_clko[0] c2 pern[5] at21 nc d31 p_ad[2] aa3 p_ad[40] aj5 p_clko[1] e1 pern[6] at23 nc d32 p_ad[3] aa1 p_ad[41] aj2 p_clko[2] c3 pern[7] at24 table 16. intel ? 81348 i/o processor 1357-lead packagealphabetical signal listings (sheet 2 of 8) signal ball signal ball signal ball signal ball signal ball
intel ? 81348datasheet intel ? 81348 i/o processor datasheet december 2007 56 order number: 315038-003us perp[0] au14 s_act5 a26 s_txp[1] c22 vcc1p2 h23 vcc1p2 p7 perp[1] au15 s_act6 f25 s_txp[2] c19 vcc1p2 j8 vcc1p2 p9 perp[2] au17 s_act7 d25 s_txp[3] c23 vcc1p2 j10 vcc1p2 p13 perp[3] au18 s_clkn0 h20 s_txp[4] c14 vcc1p2 j12 vcc1p2 p15 perp[4] au20 s_clkp0 h21 s_txp[5] c16 vcc1p2 j14 vcc1p2 p17 perp[5] au21 s_rxn[0] b20 s_txp[6] c13 vcc1p2 j18 vcc1p2 p19 perp[6] au23 s_rxn[1] b22 s_txp[7] c17 vcc1p2 j22 vcc1p2 p21 perp[7] au24 s_rxn[2] b19 scl0 at29 vcc1p2 j24 vcc1p2 r8 petn[0] ap14 s_rxn[3] b23 scl1 an29 vcc1p2 k7 vcc1p2 r10 petn[1] ap15 s_rxn[4] b14 scl2 an28 vcc1p2 k9 vcc1p2 r12 petn[2] ap17 s_rxn[5] b16 sda0 ar28 vcc1p2 k11 vcc1p2 r14 petn[3] ap18 s_rxn[6] b13 sda1 ar29 vcc1p2 k13 vcc1p2 r16 petn[4] ap20 s_rxn[7] b17 sda2 ap29 vcc1p2 k15 vcc1p2 r18 petn[5] ap21 s_rxp[0] a20 smbclk au29 vcc1p2 k17 vcc1p2 r20 petn[6] ap23 s_rxp[1] a22 smbdat au28 vcc1p2 k19 vcc1p2 t7 petn[7] ap24 s_rxp[2] a19 tck ar31 vcc1p2 k21 vcc1p2 t9 petp[0] ar14 s_rxp[3] a23 tdi au30 vcc1p2 l8 vcc1p2 t11 petp[1] ar15 s_rxp[4] a14 tdo ar30 vcc1p2 l10 vcc1p2 t13 petp[2] ar17 s_rxp[5] a16 thermda v29 vcc1p2 l12 vcc1p2 t15 petp[3] ar18 s_rxp[6] a13 thermdc v28 vcc1p2 l14 vcc1p2 t17 petp[4] ar20 s_rxp[7] a17 tms at30 vcc1p2 l16 vcc1p2 t19 petp[5] ar21 s_stat0 a25 trst# au31 vcc1p2 l18 vcc1p2 t21 petp[6] ar23 s_stat1 e25 u0_cts# a5 vcc1p2 l20 vcc1p2 u8 petp[7] ar24 s_stat2 b26 u0_rts# a6 vcc1p2 m7 vcc1p2 u10 poe# am4 s_stat3 f27 u0_rxd b6 vcc1p2 m9 vcc1p2 u12 pwe# am3 s_stat4 f26 u0_txd b5 vcc1p2 m11 vcc1p2 u14 ras# p33 s_stat5 c27 u1_cts# a4 vcc1p2 m13 vcc1p2 u16 rbias[0] e20 s_stat6 e26 u1_rts# c4 vcc1p2 m15 vcc1p2 u18 rbias[1] e15 s_stat7 d26 u1_rxd c5 vcc1p2 m17 vcc1p2 u20 rbias_sense[0] e21 s_txn[0] d20 u1_txd b4 vcc1p2 m19 vcc1p2 v7 rbias_sense[1] e16 s_txn[1] d22 vcc1p2 g8 vcc1p2 m21 vcc1p2 v9 refclkn ak19 s_txn[2] d19 vcc1p2 g10 vcc1p2 n8 vcc1p2 v11 refclkp ak20 s_txn[3] d23 vcc1p2 h7 vcc1p2 n10 vcc1p2 v13 s_act0 c26 s_txn[4] d14 vcc1p2 h9 vcc1p2 n12 vcc1p2 v15 s_act1 a27 s_txn[5] d16 vcc1p2 h11 vcc1p2 n14 vcc1p2 v17 s_act2 b25 s_txn[6] d13 vcc1p2 h13 vcc1p2 n16 vcc1p2 v19 s_act3 c25 s_txn[7] d17 vcc1p2 h17 vcc1p2 n18 vcc1p2 v21 s_act4 e27 s_txp[0] c20 vcc1p2 h19 vcc1p2 n20 vcc1p2 w8 table 16. intel ? 81348 i/o processor 1357-lead packagealphabetical signal listings (sheet 3 of 8) signal ball signal ball signal ball signal ball signal ball
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 57 datasheetintel ? 81348 vcc1p2 w10 vcc1p2 ad11 vcc1p2 aj12 vcc1p2as f22 vcc1p2x l30 vcc1p2 w12 vcc1p2 ad13 vcc1p2 aj14 vcc1p2as f23 vcc1p2x m23 vcc1p2 w14 vcc1p2 ad15 vcc1p2 aj16 vcc1p2as f24 vcc1p2x m25 vcc1p2 w16 vcc1p2 ad17 vcc1p2 aj18 vcc1p2as g22 vcc1p2x m27 vcc1p2 w18 vcc1p2 ad19 vcc1p2 aj20 vcc1p2as g23 vcc1p2x m29 vcc1p2 w20 vcc1p2 ad21 vcc1p2 aj22 vcc1p2as g24 vcc1p2x m31 vcc1p2 y7 vcc1p2 ae8 vcc1p2 ak7 vcc1p2ds e13 vcc1p2x n22 vcc1p2 y9 vcc1p2 ae10 vcc1p2 ak9 vcc1p2ds e17 vcc1p2x n24 vcc1p2 y11 vcc1p2 ae12 vcc1p2 ak11 vcc1p2ds f12 vcc1p2x n26 vcc1p2 y13 vcc1p2 ae14 vcc1p2 ak13 vcc1p2ds f14 vcc1p2x n28 vcc1p2 y15 vcc1p2 ae16 vcc1p2 ak15 vcc1p2ds g12 vcc1p2x n30 vcc1p2 y17 vcc1p2 ae18 vcc1p2 ak17 vcc1p2ds g13 vcc1p2x p23 vcc1p2 y19 vcc1p2 ae20 vcc1p2 ak21 vcc1p2e am13 vcc1p2x p25 vcc1p2 y21 vcc1p2 af7 vcc1p2 ak23 vcc1p2e am14 vcc1p2x p27 vcc1p2 aa8 vcc1p2 af9 vcc1p2 al8 vcc1p2e an13 vcc1p2x p29 vcc1p2 aa10 vcc1p2 af11 vcc1p2 al10 vcc1p2e an14 vcc1p2x p31 vcc1p2 aa12 vcc1p2 af13 vcc1p2 al12 vcc1p2e an15 vcc1p2x r22 vcc1p2 aa14 vcc1p2 af15 vcc1p2 al14 vcc1p2e an16 vcc1p2x r24 vcc1p2 aa16 vcc1p2 af17 vcc1p2 al16 vcc1p2plld ad29 vcc1p2x r26 vcc1p2 aa18 vcc1p2 af19 vcc1p2 al18 vcc1p2pllp p11 vcc1p2x r28 vcc1p2 aa20 vcc1p2 af21 vcc1p2 al22 vcc1p2plls0 j20 vcc1p2x r30 vcc1p2 ab7 vcc1p2 ag8 vcc1p2 am12 vcc1p2plls1 j15 vcc1p2x t23 vcc1p2 ab9 vcc1p2 ag10 vcc1p2 an12 vcc1p2x h25 vcc1p2x t25 vcc1p2 ab11 vcc1p2 ag12 vcc1p2 ap12 vcc1p2x h27 vcc1p2x t27 vcc1p2 ab13 vcc1p2 ag14 vcc1p2 ar12 vcc1p2x h29 vcc1p2x t29 vcc1p2 ab15 vcc1p2 ag16 vcc1p2 at12 vcc1p2x h31 vcc1p2x t31 vcc1p2 ab17 vcc1p2 ag18 vcc1p2 au12 vcc1p2x j26 vcc1p2x u22 vcc1p2 ab19 vcc1p2 ag20 vcc1p2ae am15 vcc1p2x j28 vcc1p2x u24 vcc1p2 ab21 vcc1p2 ah7 vcc1p2ae am16 vcc1p2x j30 vcc1p2x u26 vcc1p2 ac8 vcc1p2 ah9 vcc1p2ae am17 vcc1p2x k23 vcc1p2x u28 vcc1p2 ac10 vcc1p2 ah11 vcc1p2ae am18 vcc1p2x k25 vcc1p2x u30 vcc1p2 ac12 vcc1p2 ah13 vcc1p2ae am21 vcc1p2x k27 vcc1p2x v23 vcc1p2 ac14 vcc1p2 ah15 vcc1p2ae am22 vcc1p2x k29 vcc1p2x v25 vcc1p2 ac16 vcc1p2 ah17 vcc1p2ae am23 vcc1p2x k31 vcc1p2x v27 vcc1p2 ac18 vcc1p2 ah19 vcc1p2ae am24 vcc1p2x l22 vcc1p2x v31 vcc1p2 ac20 vcc1p2 ah21 vcc1p2as e22 vcc1p2x l24 vcc1p2x w22 vcc1p2 ad7 vcc1p2 aj8 vcc1p2as e23 vcc1p2x l26 vcc1p2x w24 vcc1p2 ad9 vcc1p2 aj10 vcc1p2as e24 vcc1p2x l28 vcc1p2x w26 table 16. intel ? 81348 i/o processor 1357-lead packagealphabetical signal listings (sheet 4 of 8) signal ball signal ball signal ball signal ball signal ball
intel ? 81348datasheet intel ? 81348 i/o processor datasheet december 2007 58 order number: 315038-003us vcc1p2x w28 vcc1p2x ag28 vcc1p8 w32 vcc1p8s g19 vcc3p3 am31 vcc1p2x w30 vcc1p2x ag30 vcc1p8 y32 vcc3p3 e5 vcc3p3 an5 vcc1p2x y23 vcc1p2x ah23 vcc1p8 aa32 vcc3p3 f6 pur1 an8 vcc1p2x y25 vcc1p2x ah25 vcc1p8 ab32 vcc3p3 f7 vcc3p3 an30 vcc1p2x y27 vcc1p2x ah27 vcc1p8 ac32 vcc3p3 f8 vcc3p3 an31 vcc1p2x y31 vcc1p2x ah29 vcc1p8 ad32 vcc3p3 f9 vcc3p3 ap30 vcc1p2x aa22 vcc1p2x ah31 vcc1p8 ae32 vcc3p3 f10 vcc3p3pllx y29 vcc1p2x aa24 vcc1p2x aj24 vcc1p8 af32 vcc3p3 f11 vccvio h5 vcc1p2x aa26 vcc1p2x aj26 vcc1p8 ag32 vcc3p3 f32 vccvio h6 vcc1p2x aa28 vcc1p2x aj27 vcc1p8 ah32 vcc3p3 g6 vccvio l5 vcc1p2x aa30 vcc1p2x aj28 vcc1p8 aj32 vcc3p3 g25 vccvio l6 vcc1p2x ab23 vcc1p2x aj30 vcc1p8 ak32 vcc3p3 g26 vccvio m6 vcc1p2x ab25 vcc1p2x ak25 vcc1p8 al32 vcc3p3 g27 vccvio p5 vcc1p2x ab27 vcc1p2x ak27 vcc1p8 am32 vcc3p3 g28 vccvio p6 vcc1p2x ab29 vcc1p2x ak29 vcc1p8 an32 vcc3p3 g29 vccvio u5 vcc1p2x ab31 vcc1p2x ak31 vcc1p8 ap32 vcc3p3 g30 vccvio u6 vcc1p2x ac22 vcc1p2x al24 vcc1p8 ar32 vcc3p3 g31 vccvio y6 vcc1p2x ac24 vcc1p2x al26 vcc1p8 at32 vcc3p3 g32 vccvio aa5 vcc1p2x ac26 vcc1p2x al27 vcc1p8 au32 vcc3p3 j6 vccvio aa6 vcc1p2x ac28 vcc1p2x al28 vcc1p8e am25 vcc3p3 k6 vccvio ac6 vcc1p2x ac30 vcc1p2x al30 vcc1p8e am26 vcc3p3 n6 vccvio ad5 vcc1p2x ad23 vcc1p2x am27 vcc1p8e an17 vcc3p3 r6 vccvio ad6 vcc1p2x ad25 vcc1p2x an27 vcc1p8e an18 vcc3p3 t6 vccvio af6 vcc1p2x ad27 vcc1p2x ap27 vcc1p8e an21 vcc3p3 v6 vccvio ag5 vcc1p2x ad31 vcc1p2x ar27 vcc1p8e an22 vcc3p3 w6 vccvio ag6 vcc1p2x ae22 vcc1p2x at27 vcc1p8e an23 vcc3p3 ab6 vccvio aj6 vcc1p2x ae24 vcc1p2x au27 vcc1p8e an24 vcc3p3 ae6 vccvio ak5 vcc1p2x ae26 vcc1p8 h32 vcc1p8e an25 vcc3p3 ah6 vccvio ak6 vcc1p2x ae28 vcc1p8 j32 vcc1p8e an26 vcc3p3 al6 vss a3 vcc1p2x ae30 vcc1p8 k32 vcc1p8e ap26 vcc3p3 am6 vss a35 vcc1p2x af23 vcc1p8 l32 vcc1p8e ar26 vcc3p3 am7 vss b2 vcc1p2x af25 vcc1p8 m32 vcc1p8e at26 vcc3p3 am8 vss b7 vcc1p2x af27 vcc1p8 n32 vcc1p8e au26 vcc3p3 am9 vss b10 vcc1p2x af29 vcc1p8 p32 vcc1p8s e18 vcc3p3 am10 vss b27 vcc1p2x af31 vcc1p8 r32 vcc1p8s e19 vcc3p3 am11 vss b30 vcc1p2x ag22 vcc1p8 t32 vcc1p8s f18 vcc3p3 am28 vss b36 vcc1p2x ag24 vcc1p8 u32 vcc1p8s f19 vcc3p3 am29 vss c1 vcc1p2x ag26 vcc1p8 v32 vcc1p8s g18 vcc3p3 am30 vss c34 table 16. intel ? 81348 i/o processor 1357-lead packagealphabetical signal listings (sheet 5 of 8) signal ball signal ball signal ball signal ball signal ball
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 59 datasheetintel ? 81348 vss c37 vss j34 vss m22 vss r15 vss v10 vss d4 vss j36 vss m24 vss r17 vss v12 vss d7 vss k2 vss m26 vss r19 vss v14 vss d10 vss k4 vss m28 vss r21 vss v16 vss d27 vss k8 vss m30 vss r23 vss v18 vss d30 vss k10 vss m33 vss r25 vss v20 vss e2 vss k12 vss n2 vss r27 vss v22 vss e33 vss k14 vss n4 vss r29 vss v24 vss f34 vss k16 vss n7 vss r31 vss v26 vss f36 vss k18 vss n9 vss t2 vss v30 vss g2 vss k20 vss n13 vss t4 vss v35 vss g4 vss k22 vss n15 vss t8 vss w1 vss g7 vss k24 vss n17 vss t10 vss w2 vss g9 vss k26 vss n19 vss t12 vss w4 vss g11 vss k28 vss n21 vss t14 vss w7 vss h8 vss k30 vss n23 vss t16 vss w9 vss h10 vss k34 vss n25 vss t18 vss w11 vss h12 vss k36 vss n27 vss t20 vss w13 vss h14 vss l7 vss n29 vss t22 vss w15 vss h15 vss l9 vss n31 vss t24 vss w17 vss h16 vss l11 vss n34 vss t26 vss w19 vss h18 vss l13 vss n36 vss t28 vss w21 vss h22 vss l15 vss p8 vss t30 vss w23 vss h24 vss l17 vss p10 vss t34 vss w25 vss h26 vss l19 vss p12 vss t36 vss w27 vss h28 vss l21 vss p14 vss u7 vss w31 vss h30 vss l23 vss p16 vss u9 vss w33 vss j7 vss l25 vss p18 vss u11 vss y8 vss j9 vss l27 vss p20 vss u13 vss y10 vss j11 vss l29 vss p22 vss u15 vss y12 vss j13 vss l31 vss p24 vss u17 vss y14 vss j17 vss m8 vss p26 vss u19 vss y16 vss j19 vss m10 vss p28 vss u21 vss y18 vss j23 vss m12 vss p30 vss u23 vss y20 vss j25 vss m14 vss r7 vss u25 vss y22 vss j27 vss m16 vss r9 vss u27 vss y24 vss j29 vss m18 vss r11 vss u31 vss y26 vss j31 vss m20 vss r13 vss v8 vss y28 table 16. intel ? 81348 i/o processor 1357-lead packagealphabetical signal listings (sheet 6 of 8) signal ball signal ball signal ball signal ball signal ball
intel ? 81348datasheet intel ? 81348 i/o processor datasheet december 2007 60 order number: 315038-003us vss y30 vss ac21 vss af14 vss aj7 vss al33 vss y35 vss ac23 vss af16 vss aj9 vss am34 vss aa7 vss ac25 vss af18 vss aj11 vss am36 vss aa9 vss ac27 vss af20 vss aj13 vss ap4 vss aa11 vss ac31 vss af22 vss aj15 vss ap7 vss aa13 vss ad8 vss af24 vss aj17 vss ap10 vss aa15 vss ad10 vss af26 vss aj19 vss ap28 vss aa17 vss ad12 vss af28 vss aj21 vss ap31 vss aa19 vss ad14 vss af30 vss aj23 vss ar1 vss aa21 vss ad16 vss ag7 vss aj25 vss ar34 vss aa23 vss ad18 vss ag9 vss aj29 vss ar37 vss aa25 vss ad20 vss ag11 vss aj31 vss at2 vss aa27 vss ad22 vss ag13 vss aj34 vss at7 vss aa29 vss ad24 vss ag15 vss aj36 vss at10 vss aa31 vss ad26 vss ag17 vss ak8 vss at28 vss ab2 vss ad28 vss ag19 vss ak10 vss at31 vss ab4 vss ad30 vss ag21 vss ak12 vss at36 vss ab8 vss ad33 vss ag23 vss ak14 vss au3 vss ab10 vss ae2 vss ag25 vss ak16 vss au33 vss ab12 vss ae4 vss ag27 vss ak18 vss au34 vss ab14 vss ae7 vss ag29 vss ak22 vss au35 vss ab16 vss ae9 vss ag31 vss ak24 vssas a12 vss ab18 vss ae11 vss ah2 vss ak26 vssas a15 vss ab20 vss ae13 vss ah4 vss ak28 vssas a18 vss ab22 vss ae15 vss ah8 vss ak30 vssas a21 vss ab24 vss ae17 vss ah10 vss al2 vssas a24 vss ab26 vss ae19 vss ah12 vss al4 vssas b12 vss ab28 vss ae21 vss ah14 vss al7 vssas b15 vss ab30 vss ae23 vss ah16 vss al9 vssas b18 vss ab34 vss ae25 vss ah18 vss al11 vssas b21 vss ab36 vss ae27 vss ah20 vss al13 vssas b24 vss ac7 vss ae29 vss ah22 vss al15 vssas c12 vss ac9 vss ae31 vss ah24 vss al17 vssas c15 vss ac11 vss ae34 vss ah26 vss al21 vssas c18 vss ac13 vss ae36 vss ah28 vss al23 vssas c21 vss ac15 vss af8 vss ah30 vss al25 vssas c24 vss ac17 vss af10 vss ah34 vss al29 vssas d12 vss ac19 vss af12 vss ah36 vss al31 vssas d15 table 16. intel ? 81348 i/o processor 1357-lead packagealphabetical signal listings (sheet 7 of 8) signal ball signal ball signal ball signal ball signal ball
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 61 datasheetintel ? 81348 vssas d18 vsse ap13 vsse ar25 vsse au22 xint#[0] b8 vssas d21 vsse ap16 vsse at13 vsse au25 xint#[1] a9 vssas d24 vsse ap19 vsse at16 vssplld ac29 xint#[2] a8 vssds e12 vsse ap22 vsse at19 vsspllp n11 xint#[3] b9 vssds e14 vsse ap25 vsse at22 vssplls0 j21 xint#[4] d9 vssds f13 vsse ar13 vsse at25 vssplls1 j16 xint#[5] c9 vssds f17 vsse ar16 vsse au13 vsspllx u29 xint#[6] c8 vssds g14 vsse ar19 vsse au16 warm_rst# e4 xint#[7] e9 vssds g17 vsse ar22 vsse au19 we# l33 a. ma[14] is only needed for 4gb memory support. when 4gb memory is not used this pin is nc. table 16. intel ? 81348 i/o processor 1357-lead packagealphabetical signal listings (sheet 8 of 8) signal ball signal ball signal ball signal ball signal ball
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 62 order number: 315038-003us 4.0 electrical specifications table 17. absolute maximum ratings parameter maximum rating notice: this data sheet contains informa- tion on products in the design phase of development. do not finalize a design with this informa- tion. revised information will be published when the product becomes available. the specifica- tions are subject to change without notice. contact your local intel rep- resentative before finalizing a design. storage temperature C10c to +45c supply voltage v cc3p3 wrt. v ss C0.5 v to +4.1 v supply voltage v cc1p8s wrt. v ssas C0.5 v to +2.5 v supply voltage v cc1p8e wrt. v sse C0.5 v to +2.5 v supply voltage v cc1p8 wrt. v ss C0.5 v to +2.5 v supply voltage v ccvio wrt. v ss C0.5 v to +4.1 v supply voltage v cc1p2x wrt. v ss C0.5 v to +1.8 v supply voltage v cc1p2 wrt. v ss C0.5 v to +1.8 v supply voltage v cc1p2ae wrt. v sse C0.5 v to +1.8 v supply voltage v cc1p2e wrt. v sse C0.5 v to +1.8 v supply voltage v cc1p2as wrt. v ssas C0.5 v to +1.8 v supply voltage v cc1p2ds wrt. v ssds C0.5 v to +1.8 v voltage on any ball wrt. v ss C0.5 v to v ccp +0.5 v ? warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 63 electrical specificationsintel ? 81348 table 18. operating conditions symbol parameter minimum maximum units notes v cc3p3 3.3 v supply voltage for pci-x category 2 signals and general purpose i/os 3.0 3.6 v v cc1p8s 1.8 v supply voltage for storage interface 1.71 1.89 v v cc1p8e 1.8 v supply voltage for pci express* interface 1.71 1.89 v v cc1p8 1.8 v supply voltage for ddr2 sdram memory interface i/os 1.71 1.89 v v ccvio 3.3 v supply voltage for pci-x category 1 signals 3.0 3.6 v v cc1p2x 1.2 v supply voltage for intel xscale ? processors 1.164 1.236 v v cc1p2 1.2 v supply voltage for most digital logic 1.164 1.236 v v cc1p2e 1.2 v supply voltage for pci express* interface digital logic 1.164 1.236 v v cc1p2ae 1.2 v supply voltage for pci express* interface analog logic 1.164 1.236 v v cc1p2as 1.2 v supply voltage for storage interface analog logic 1.164 1.236 v v cc1p2ds 1.2 v supply voltage for storage interface digital logic 1.164 1.236 v v cc1p2plls0 1.2 v supply voltage for storage pll 0 1.164 1.236 v v cc1p2plls1 1.2 v supply voltage for storage pll 1 1.164 1.236 v v cc1p2pllp 1.2 v supply voltage for pci-x pll 1.164 1.236 v v cc1p2plld 1.2 v supply voltage for ddr2 sdram pll processor logic pll. 1.164 1.236 v v cc3p3pllx 3.3 v supply voltage for processor logic pll 3.0 3.6 v m_vref memory i/o reference voltage 0.49 v cc1p8 0.51 v cc1p8 v t c case temperature under bias 0100c
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 64 order number: 315038-003us 4.1 v ccpll pin requirements to reduce clock jitter, the v cc1p2plld , v cc1p2pllp , and v cc3p3pllx , v cc1p2plls0 and v cc1p2plls1 balls for the phase-lock loop (pll) circuits are isolated on the package. the low-pass filters, as shown in the following figures, reduce noise-induced clock jitter and its effects on timing relationships in system design. this paragraph pertains to the v cc1p2plld , v cc1p2pllp , v cc3p3pllx filters. the filter components must be able to handle a dc current of 30 ma. use a shielded type inductor to minimize magnetic pickup. the total series resistance from the board vcc plane (before the filter) to the vccpll ball must be less than 1.5 ohm (including component and trace resistance). the total series resistance from the board vcc plane (before the filter) to the top plate of the capacitor must be greater than 0.35 ohm (including component and trace resistance). the nodes connecting vccpll and vsspll to the capacitor must be as short as possible (less than 0.1 w). vccpll and vsspll must be routed close to each other to minimize loop area. the vsspll balls must be connected to the filter only and not to any other ground, as shown in figure 7 and figure 9 . the inductor and capacitor must be placed close to each other. any discrete resistor must be placed between the vcc board plane and the inductor. if the trace and component resistance is high enough, a discrete resistor might not be required. this paragraph pertains to the v cc1p2plls0 , v cc1p2plls1 filters. the recommended filter for the pll supplies is shown in figure 8 . the purpose of this filter is to achieve at least 10 db rejection of frequencies between 1 and 20 mhz. the current draw for the ic is less than 85 ma. the boards supply distribution system must ensure that the minimum voltage into the filter is equal to or greater than 1.14 v. the filter components are selected to achieve a corner frequency of 100 khz. the series resistance keeps the q of this resonant circuit safely below unity for all component variations. the bypass capacitor must be placed as close to the supply pins as possible. the series impedances to both the supply pin and the pcb analog ground plane must be an order of magnitude lower than the esr and esl specified for the capacitor. the s0/s1 plls have dedicated internal supplies, so the vssplls0/s1 pins must be soldered directly to the analog ground plane of the pcb. figure 7. v cc3p3pllx low-pass filter 3.3v (board plane) 22 f 20%, esr < 0.3, 4.7 uh, 25% v sspllx 6.3 v, esl < 2.5nh (not connected to board ground) v cc3p3pllx
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 65 electrical specificationsintel ? 81348 figure 8. v cc1p2plls0 , v cc1p2plls1 low-pass filter figure 9. v cc1p2plld , v cc1p2pllp low-pass filter 0.1 ? , 5% (board plane) 22 f, 20%, esr < 0.3, 120 nh, 20% rdc max < 0.3 1.2v vssplls0/1 45 ma 6.3 v, esl < 2.5nh (board ground) v cc1p2plls0/1 (board plane) 22 f, 20%, esr < 0.3, 4.7 uh, 25% 1.2v 6.3 v, esl < 2.5nh (not connected to board ground) v ssplld / v sspllp v cc1p2plld / v cc1p2pllp
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 66 order number: 315038-003us 4.2 targeted dc specifications table 19. dc characteristics symbol parameter minimum maximum units notes v il1 input low voltage (general purpose). -0.3 0.3 v cc3p3 v 2 v ih1 input high voltage (general purpose). 2.0 v cc3p3 + 0.3 v 2 v il2 input low voltage (pci). -0.5 0.3 v cc3p3 v v il3 input low voltage (pci-x). -0.5 0.35 v cc3p3 v v ih3 input high voltage (pci-x/pci). 0.5 v cc3p3 v cc3p3 + 0.5 v v il4 input low voltage (ddr2 sdram). -0.3 m_vref - 0.125 v v ih4 input high voltage (ddr2 sdram). m_vref + 0.125 v cc1p8 + 0.3 v v ol1 output low voltage (general purpose). C0.4 v i ol = 10 ma 2 v oh1 output high voltage (general purpose). 2.6 C v i oh = -10 ma 2 v ol2 output low voltage (pci-x). C0.1 v cc3p3 v i ol = 1.50 ma v oh2 output high voltage (pci-x). 0.9 v cc3p3 C v i oh = -0.50 ma v ol3 output low voltage (ddr2 sdram driver set to 21 ? ). 0.28 v i ol = 11 ma v oh3 output high voltage (ddr2 sdram driver set to 21 ? ). 1.42 v i oh = -11 ma v ol4 output low voltage (ddr2 sdram driver set to 50 ? ). 0.28 v i ol = 5 ma v oh4 output high voltage (ddr2 sdram driver set to 50 ? ). 1.42 v i oh = -5 ma i li1 input leakage current for general purpose pins when internal pull up resistors are not enabled. 5 a 0 v in v cc3p3 3 i li2 input leakage current for pci-x pins when internal pull up resistors are not enabled. 10 a 0 v in v cc3p3 (cat . 2) 0 v in v ccvio (cat. 1) 3 i li3 input leakage current for ddr2 pins when internal pull up resistors are not enabled. 2 a 0 v in v cc1p8 3 r gp internal pull up resistor value for general purpose pins. 28.5 38.7 ? 1 r pcix internal pull up resistor value for pci-x pins. 5.9 8.1 ? 1 c gp general purpose pin capacitance. 1 4.5 pf 1 c pcix pci-x pin capacitance. 1 4.5 pf 1 c ddr2 ddr2 pin capacitance. 1 4.5 pf 1 l pin ball inductance. 112nh 1 notes: 1. not tested, guaranteed by design. 2. general purpose signals include all signals that are not part of the ddr2, pci-x and pci-express interfaces or the storage tx/rx pairs and analog pins. 3. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 67 electrical specificationsintel ? 81348 table 20. i cc characteristics symbol parameter typ max units notes icc12 active (power supply) power supply current: storage phy, pci express, intel xscale ? michroarchitecture: ?800mhz ? 1200mhz 7.83 8.39 a 1 , 2 , 4 icc18 active (power supply) power supply current: storage phy i/os, pci express i/os, ddr-ii (533) 1.71 a 1 , 2 , 4 icc33 active (power supply) power supply current: pci, pbi, gpio, pci-x i/os 0.69 a 1 , 2 icc12 active (thermal) thermal current: storage phy, pci express, intel xscale ? microarchitecture: ?800mhz ? 1200mhz 5.55 6.81 a 1 , 3 , 4 icc18 active (thermal) thermal current: storage phy i/os, pci express i/os, ddr-ii (533) 1.40 a 1 , 3 , 4 icc33 active (thermal) thermal current: pci, pbi, gpio, pci-x i/os 0.60 a 1 , 3 notes: 1. measured with the device operating and outputs loaded to the test condition in figure 17, ac test load for all signals except pci, pci-express and ddr2 and storage phy on page 82 . 2. icc active (power supply) value is provided for selecting the system power supply. this is based on the worst case data patterns and skew material at the following worst case voltages: vcc33 = 3.63 v, vcc18 = 1.89 v, vcc12 = 1.24 v and ambient temperature = 55c. 3. icc active (thermal) value is provided for selecting the system thermal design power (tdp). this is based on the following typical voltages: vcc33 = 3.3 v, vcc18 = 1.8v, vcc12 = 1.2 v and ambient temperature = 55c. 4. the customer reference boards use a 1.2 v switching regulator for all the 1.2 v supplies (vcc1p2, vcc1p2x, vcc1p2e, vcc1p2ds, vcc1p2ae, vcc1p2as) and a 1.8 v switching regulator for all 1.8 v supplies: (vcc1p8, vcc1p8e, vcc1p8s).
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 68 order number: 315038-003us 4.3 targeted ac specifications 4.3.1 clock signal timings table 21. pci clock timings symbol parameter pci-x 133 pci-x 100 pci-x 66 pci 66 pci 33 units notes min. max min. max min. max min. max min. max t c1 pci clock cycle time jitter class 1 7.5 11 10 15 152215253050 ns 1 t c2 pci clock cycle time jitter class 2 7.375 11 9.875 15 14.8 22 14.8 25 29.7 50 1 t ch1 pci clock high time 2.5 3 5.5 5.5 10 ns tcl1 pci clock low time 2.5 3 5.5 5.5 10 ns pci clock period jitter 125 -125 125 -125 200 -200 200 -200 300 -300 ps 3 tsr1 pci clock slew rate 1.5 4 1.5 4 1.5 4 1.5 4 1 4 v/ns 2 pci spread spectrum requirements f mod pci clock modulation frequency 30 33 30 33 30 33 30 33 khz f spread pci clock frequency spread -10-10-10-10 % pci output clocks pci output clock skew 250 350 350 350 350 ps pci output clock period jitter 100 -100 150 -150 150 -150 150 -150 150 -150 ps 4, 5 notes: 1. the clock frequency may not change beyond the spread-spectrum limits except while p_rst# or warm_rst# is asserted. 2. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform. 3. period jitter is the deviation between any single period of the clock and the average period of the clock. 4. if a jitter class 2 input clock is used, output clocks can not support jitter class 1. 5. the deviation between any single period of the clock and the average period of the clock.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 69 electrical specificationsintel ? 81348 table 22. pci express clock timings symbol parameter min. nom. max. units notes tf2 pci express* clock frequency 100 mhz 4 tc2 pci express* clock cycle time 9.872 ns df0 frequency variation -300 300 ppm tccj cycle to cycle jitter 125 ps tppj peak to peak jitter (5C50 mhz) 50 ps dc clock duty cycle 45 55 % trise refclk rise time 175 350 ps 1 , 2 , 6 tfall refclk fall time 175 350 ps 1 , 2 , 6 tvrise refclk rise time variation 125 ps tvfall refclk fall time variation 125 ps rise-fall matching 20 % vca absolute cross point 0.25 0.55 v 1 , 3 , 7 , 13 vcr relative cross point calc calc 5 , 12 tvc total variation of vc over all edges 0.14 v 13 rising edge ringback 0.56 v absolute min. falling edge ringback 0.25 v absolute max. vhi high level voltage 0.66 0.71 0.85 v 7 , 8 vli low level voltage -0.15 0 0.15 v 7 , 9 vrb ringback voltage 0.10 v 7 vovs maximum overshoot vhi+0.3 v 7 , 10 vuds minimum undershoot -0.30 v 7 , 11 notes: 1. measured at crossing point where the instantaneous voltage value of the rising edge of refclk equals the falling edge of refclk#. 2. measured from v ol = 0.175 v to v oh = 0.525 v. valid only for rising refclk and falling refclk#. signal must be monotonic through the v ol to v oh region for t rise and t fall . 3. this measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. 4. the average period over any 1 s period of time must be greater than the minimum specified period. 5. v cross (rel) min and max are derived using the following: v cross (rel) min = 0.5 (v havg - 0.710) + 0.250 v cross (rel) max = 0.5 (v havg - 0.710) + 0.550 6. measurement taken from single-ended waveform. 7. measurement taken from differential waveform. 8. v high is defined as the statistical average high value as obtained by using the osc illoscope v high math function. 9. v low is defined as the statistical average low value as obtained by using the osc illoscope v low math function. 10. overshoot is defined as the absolute value of the maximum voltage. 11. undershoot is defined as the absolute value of the minimum voltage. 12. the crossing point must meet the absolute and relative crossing point specifications simultaneously. 13. ? v cross is defined as the total variation of all crossing voltages of rising refclk and falling refclk#. this is the maximum allowed variance in v cross for any particular system. 14. refer to section 4.3.2.1 in the pci express base specification for information regarding ppm considerations.
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 70 order number: 315038-003us table 23. ddr2 output clock timings symbol parameter ddr2-400 ddr2-533 unit s note s min. max min. max t c2 ddr2 sdram clock cycle time average 5.00 3.75 ns t ch2 ddr2 sdram clock high time 2.25 1.69 ns t cl2 ddr2 sdram clock lowtime 2.25 1.69 ns t cs2 ddr2 sdram clock period jitter 100 -100 100 -100 ps t skew2 ddr2 sdram clock skew for any differential clock pair to any other clock pair 250 250 ps t skew3 ddr2 sdram clock skew for any clock pair to any system memory strobe 250 250 ps notes: 1. not tested
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 71 electrical specificationsintel ? 81348 4.3.2 ddr2 sdram interface signal timings table 24. ddr2 sdram signal timings symbol parameter min. max units notes tvb1 dq, cb and dm write output valid time before dqs 0.530 ns 1, 3 tva1 dq, cb and dm write output valid time after dqs 0.530 ns 1, 3 tvb2 dqs write output valid time before m_ck (dqs early) 0.200 ns 1, 3 tva2 dqs write output valid time after m_ck (dqs late) 0.530 ns 1, 3 tv b 3 ma, ba, ras# , cas# , we# write output valid before m_ck rising edge. 4.900 ns 1, 3 tva 3 ma, ba, ras# , cas# , we# write output valid after m_ck rising edge. 1.530 ns 1, 3 tv b 4 cs#, cke, odt write output valid before m_ck rising edge. unbuffered mode 2.090 ns 1, 3 tva 4 cs#, cke, odt write output valid after m_ck rising edge. unbuffered mode 0.590 ns 1, 3 tv b 5 cs#, cke, odt write output valid before m_ck rising edge. registered mode 1.150 ns 1, 3 tva 5 cs#, cke, odt write output valid after m_ck rising edge. registered mode 1.530 ns 1, 3 tis6 dq, cb read input setup time before dqs rising or falling edges. -0.670 ns 2 tih6 dq, cb read input hold time after dqs rising or falling edges. 1.250 ns 2 to v 7 m_ck[2:0] output valid from p_clkin or refclk 0.460 1.930 ns notes: 1. see figure 14, ddr2 sdram write timings on page 81 . 2. see figure 16, ddr2 sdram read timings on page 82 . timings valid when the dqs delay is programmed for the default 90 degree phase shift. 3. see figure 18, ac test load for ddr2 sdram signals on page 82 .
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 72 order number: 315038-003us 4.3.3 peripheral bus interface signal timings table 25. peripheral bus interface signal timings symbol parameter min. nom. max. units a2d address to data wait-states 4 - 20 clks d2d data to data wait-states 4 - 20 clks rec recovery wait-states 1 - 20 clks n number of data phases 1 - 4 phases tasc address setup to ce# 25 30 - ns taso address setup to oe# 10 15 - ns tasw address setup to we# 25 30 - ns tah address hold from ce#,oe# nom - 5 rec 15 - ns tahw address hold from we# nom - 5 (rec+1) 15 - ns twce ce# pulse width nom - 5 (a2d + 2 + ((n - 1)(d2d + 2))) 15 -ns twoe oe# pulse width nom - 5 (a2d + 3 + ((n - 1)(d2d + 2))) 15 -ns twwe we# pulse width nom - 5 (a2d + 1) 15 - ns tdsw write data setup to we# nom - 5 (a2d + 1) 15 - ns tdhw write data hold from we# 10 15 20 ns tad1 1st read data access time from address - (a2d + 4) 15 nom - 11 ns tadn nth read data access time from address - (d2d + 2) 15 nom - 11 ns tcd read data access time from ce# - (a2d + 2) 15 nom - 11 ns toe read data access time from oe# 0 (a2d + 3) 15 nom - 11 ns tdh read data hold time from address, ce#, oe# 0 (rec + 2) 15 nom - 5 ns notes: 1. see figure 25, pbi output timings on page 85 and figure 26, pbi external device timings (flash) on page 86 .
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 73 electrical specificationsintel ? 81348 4.3.4 i 2 c/smbus interface signal timings table 26. i 2 c/smbus signal timings symbol parameter std. mode fast mode units note s min. max min. max fscl scl clock frequency 0 100 0 400 khz t buf bus free time between stop and start condition 4.7 1.3 s(1) t hdsta hold time (repeated) start condition 4 0.6 s(1,3) t low scl clock low time 4.7 1.3 s(1,2) thigh scl clock high time 4 0.6 s(1,2) tsusta setup time for a repeated start condition 4.7 0.6 s(1) thddat data hold time 0 3.45 0 0.9 s(1) tsudat data setup time 250 100 ns (1) t sr scl and sda rise time 1000 20 + 0.1c b 300 ns (1,4) t sf scl and sda fall time 300 20 + 0.1c b 300 ns (1,4) t susto setup time for stop condition 4 0.6 s(1) notes: 1. see figure 13, i 2 c interface signal timings on page 80 . 2. not tested. 3. after this period, the first clock pulse is generated. 4. c b = the total capacitance of one bus line, in pf. 5. std mode i 2 c signal timings apply for smbus timing.
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 74 order number: 315038-003us 4.3.5 pci bus interface signal timings table 27. pci signal timings symbol parameter pci-x 133 pci-x 100 pci-x 66 pci 66 pci 33 units notes min. max min. max min. max min. max t ov1 clock to output valid delay 0.7 3.7 0.7 3.7 1 6 2 11 ns 1, 3 t of clock to output float delay 7 7 14 28 ns 1, 4 t is1 input setup to clock 1.2 1.7 3 7 ns 2 t ih1 input hold time from clock 0.5 0.5 0 0 ns 2 t rst reset active time 1111 ms t rf reset active to output float delay 40 40 40 40 ns t is3 req64# to reset setup time 10 10 10 10 clocks t ih2 reset to req64# hold time 0 50 0 50 0 50 0 50 ns t is4 pci-x initialization pattern to reset setup time 10 10 clocks t ih3 reset to pci-x initialization pattern hold time 050050 ns notes: 1. see the timing measurement conditions in; figure 11, output timing measurement waveforms on page 79 . 2. see the timing measurement conditions in: figure 12, input timing measurement waveforms on page 80 . 3. see figure 19, pci/pci-x tov(max) rising edge ac test load on page 83 , figure 20, pci/pci-x tov(max) falling edge ac test load on page 83 , figure 21, pci/pci-x tov(min) ac test load on page 83 . 4. for purposes of active/float timing measurements, the hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 75 electrical specificationsintel ? 81348 4.3.6 pci express differential transmitter (tx) output specifications table 28. pci express* rx input specifications symbol parameter min. nom max units notes v diffp-p differential input voltage 0.175 1.200 v 1 j total total output jitter 0.65 ui 2 v cm-ac ac common mode 100 mv 3 t reye receiver eye opening 0.35 ui 4 rl-diff rx differential return loss 12 db 5 rl-cm tx common mode return loss 6 db 5 z rx-out-dc dc differential output impedance 90 100 110 ohm 6 z rx-match-dc d+/d- impedance matching -5 +5 % 7 v rx-squelch squelch detect threshold 75 175 mv 8 cin rx ac coupled 75 nf 9 l skew-rx lane to lane skew at rx 20 ui 10 notes: 1. peak-peak differential voltage. v diffp-p = 2 v rmax. measured at the package pins of the receiver. see figure 12 . 2. max jitter tolerated by rx. this is the nominal value tolerated at the package pin of the receiver device. a receiver must therefore tolerate any additional jitter generated by the package to the die. 3. peak common mode value. |v d+ + v d- |/2 - v cm-dc(avg) 4. see figure 24, receiver eye opening (differential) on page 84 . 5. 50 mhz to 1.6 ghz. the driver output impedance shall result in a differential return loss greater than or equal to 15 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.8 ghz. this output impedance requirement applies to all valid output levels. the reference impedance for return loss measurements is 100 ? for differential return loss and 25 ? for common mode (i.e. as measured by a vector network analyzer with 100 ? differential probes). note this is based on a nominal pci express* interconnect differential characteristic impedance of 100 ? . applicable during active (l0) and align states only. 6. dc differential mode impedance 100 ? 10% tolerance. 7. dc impedance matching between two lanes of a port. 8. peak-to-peak value. measured at the pin of the receiver. differential signal below this level w ill indicate a squelch condition. 9. all receivers shall be ac coupled to the media. 10. lane skew at the receiver that must be tolerated.
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 76 order number: 315038-003us table 29. pci express* tx output specifications symbol parameter min. nom max units notes ui unit interval 400 ps 1 v diffp-p differential output voltage 0.800 1.200 v 2 t rise , t fall driver rise/fall time 0.2 0.4 ui 3 v tx-cm-ac ac common mode 20 mv 4 v tx-cm-dc delta common mode active to sleep mode delta -50 +50 mv rl-diff tx differential return loss 15 db 5 rl-cm tx common mode return loss 6 db 5 z tx-out-dc dc differential output impedance 90 100 110 ? 6 z tx-match-dc d+/d- impedance matching -5 +5 % 7 l skew-tx lane to lane skew at tx 500 ps 8 j total total output jitter. 0.35 ui 9 t deye minimum transmitter eye opening. 0.65 ui 10 i tx-short short circuit current -100 100 ma 11 v tx-idle sleep mode voltage output 0 0 20 mv 12 notes: 1. 300 ppm. ui does not account for ssc dictated variations. no test load is necessarily associated with this value. this ui specification is a before transmission specification and represents the nominal time of each bit transmission or width. 2. peak-peak differential voltage. v diffp-p = 2 v dmax. specified at the package pins into a 100 ? test load as shown in figure 22, transmitter test load (100 ? diff load) on page 83 . max level set by maximum single ended voltage after a reflection from an open. this value is for the first bit after a transition on the data lines. subsequent bits of the same polarity shall have an amplitude of 6 db (0.5 db) less as measured differentially peak to peak than the specified value. 3. 20C80% at transmitter. slower rise/fall times are better. 4. peak common mode value. |v d+ + v d- |/2 - v cm-dc(avg) 5. 50 mhz to 1.6 ghz. the driver output impedance shall result in a differential return loss greater than or equal to 15 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.8 ghz. this output impedance requirement applies to all valid output levels. the reference impedance for return loss measurements is 100 ? for differential return loss and 25 ? for common mode (i.e. as measured by a vector network analyzer with 100 ? differential probes). note this is based on a nominal pci express* interconnect differential characteristic impedance of 100 ? . applicable during active (l0) and align states only. 6. dc differential mode impedance 100 ? 10% tolerance. all devices shall employ on-chip adaptive impedance matching circuits to ensure the best possible termination/zout for its transmitters (as well as receivers). 7. dc impedance matching between two lanes of a port. 8. between any two lanes within a single transmitter. 9. clock source ppm mismatch is in addition to this value. measured over 250 ui. 10. see figure 23, transmitter eye diagram on page 84 . 11. between any voltage from max supply to gnd with power on or off. 12. squelch condition. both signals brought to v cm-dc-|vd+ - vd-|
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 77 electrical specificationsintel ? 81348 4.3.7 pci express* differential receiver (rx) input specifications table 30. pci express* rx input specifications symbol parameter min. nom max units notes v diffp-p differential input voltage 0.175 1.200 v 1 j total total output jitter. 0.65 ui 2 v cm-ac ac common mode 100 mv 3 t reye receiver eye opening. 0.35 ui 4 rl-diff rx differential return loss 15 db 5 rl-cm tx common mode return loss 6 db 5 z rx-out-dc dc differential output impedance 90 100 110 ? 6 z rx-match-dc d+/d- impedance matching 0-5 +5 % 7 v rx-squelch squelch detect threshold 75 175 mv 8 cin rx ac coupled 400 pf 9 l skew-rx lane to lane skew at rx 20 ui 10 notes: 1. peak-peak differential voltage. v diffp-p = 2 * v rmax. measured at the package pins of the receiver. see figure 12 . 2. max jitter tolerated by rx. this is the nominal value tolerated at the package pin of the receiver device. a receiver must therefore tolerate any additional jitter generated by the package to the die. 3. peak common mode value. |v d+ + v d- |/2 - v cm-dc(avg) 4. see figure 24, receiver eye opening (differential) on page 84 . 5. 50 mhz to 1.6 ghz. the driver output impedance shall result in a differential return loss greater than or equal to 15 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.8 ghz. this output impedance requirement applies to all valid output levels. the reference impedance for return loss measurements is 100 ? for differential return loss and 25 ? for common mode (i.e. as measured by a vector network analyzer with 100 ? differential probes). note this is based on a nominal pci express* interconnect differential characteristic impedance of 100 ? . applicable during active (l0) and align states only. 6. dc differential mode impedance 100 ? 10% tolerance. 7. dc impedance matching between two lanes of a port. 8. peak to peak value. measured at the pin of the receiver. differential signal below this level will indicate a squelch condition. 9. all receivers shall be ac coupled to the media. 10. lane skew at the receiver that must be tolerated.
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 78 order number: 315038-003us 4.3.8 boundary scan test signal timings table 31. boundary scan test signal timings symbol parameter min. max units notes t jtf tck frequency 0 66 mhz t jtch tck high time 7.0 ns measured at 1.5 v (1) tjtcl tck low time 7.0 ns measured at 1.5 v (1) t jtcr tck rise time 5 ns 0.8 v to 2.0 v (1) t jtcf tck fall time 5 ns 2.0 v to 0.8 v (1) t jtis1 input setup to tck tdi , tms 3.0 ns (3) t jtih1 input hold from tck tdi , tms 2.0 ns (3) t jtov1 tdo output valid delay 4.25 13.25 ns relative to falling edge of tck (2) t of1 tdo float delay 4.25 13.25 ns relative to falling edge of tck (4) notes: 1. not tested. 2. see figure 11, output timing measurement waveforms on page 79 . 3. see figure 12, input timing measurement waveforms on page 80 . 4. a float condition occurs when the output current becomes less than i lo . float delay is not tested. see figure 11, output timing measurement waveforms on page 79 .
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 79 electrical specificationsintel ? 81348 4.4 ac timing waveforms figure 10. clock timing measurement waveforms figure 11. output timing measurement waveforms tch tcl tc vtc h vih(min) vil(max) vtest vtc l vtest clk output float vtrise output delay rise output delay fall vtfall to v1 tov1 to f v tl v th
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 80 order number: 315038-003us figure 12. input timing measurement waveforms figure 13. i 2 c interface signal timings clk input val id v test v test v test t is1 t ih1 vtl vth vth vtl vmax sd a scl t bu f stop start t lo w t hd s t a t high t sr t hddat t sf t sudat t sus ta repeated t hd sta t sp sto p t susto start
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 81 electrical specificationsintel ? 81348 figure 14. ddr2 sdram write timings figure 15. dqs falling edge output access time to/from m_ck rising edge m_ck dq s dq t va 1 t vb1 t vb 4/5 t va4/5 cs # t vb3 t va3 addr/cmd dqs# m_ck dqs max dqs min tvb2 tva2
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 82 order number: 315038-003us figure 16. ddr2 sdram read timings table 32. ac measurement conditions symbol pci-x pci ddr2 pbi units notes vth 0.6 v cc3p3 0.6 v cc3p3 m_vref +0.250 2.0 v v tl 0.25 v cc3p3 0.2 v cc3p3 m_vref -0.250 0.8 v v test 0.4 v cc3p3 0.4 v cc3p3 0.5 v cc1p8 1.5 v v trise 0.285 v cc3p3 0.285 v cc3p3 0.5 v cc1p8 1.5 v v tfall 0.615 v cc3p3 0.615 v cc3p3 0.5 v cc1p8 1.5 v v max 0.35 v cc3p3 0.4 v cc3p3 1.0 1.2 v slew rate 1.5 1.5 1.0 1.0 v/ns 1 notes: 1. input signal slew rate is measured between v il and v ih figure 17. ac test load for all signals except pci, pci-express and ddr2 and storage phy figure 18. ac test load for ddr2 sdram signals dqs d q t vb6 t va6 output 50 pf tes t poin t 25 ? v tt output te s t point
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 83 electrical specificationsintel ? 81348 figure 19. pci/pci-x t ov(max) rising edge ac test load figure 20. pci/pci-x t ov(max) falling edge ac test load figure 21. pci/pci-x t ov(min) ac test load figure 22. transmitter test load (100 ? diff load) output te st point 10 pf 25 ? output 10 pf 25 ? v cc33 tes t poin t output te s t point 10 pf 1k ? 1k ? v cc33 d+ d- + - v cm-dc 50 ? 50 ?
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 84 order number: 315038-003us figure 23. transmitter eye diagram figure 24. receiver eye opening (differential) note: transmitter vdiffp-p = 2 * vdmax ui vdmax vdmin tdeye note: transmitter vdiffp-p = 2 * vrmax ui vrmax vrmin treye
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 85 electrical specificationsintel ? 81348 figure 25. pbi output timings pbi_clk a ce# oe# data(rd) address aawn...woddwm...woddrn...ro address++ dd a2d w/s d2d w/s recovery w/s read pbi_clk a ce# address a a wn ... wo d d rn ... ro we# data(wr) a2d w/s recovery w/s write tasc taso twoe twce tah twwe tdsw tdhw tasw tahw pbi output timings - read pbi output timings - write notes: (1) pbi_clk is provided as a virtual clock and is not available as an external signal. (2) d2d wait state register is not available until b-step. a2d must be used for this value for a-step. (3) timings are based on 66 mhz pbi_clk.
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 86 order number: 315038-003us figure 26. pbi external device timings (flash) pbi_clk a ce# oe# data(rd) address aawn...woddwm...woddrn...ro address++ dd a2d w/s d2d w/s recovery w/s read tad1 tcd toe tdh tdh tadn pbi external device timings (flash) notes: (1) pbi_clk is provided as a virtual clock and is not available as an external signal. (2) d2d wait state register is not available until b-step. a2d must be used for this value for a-step. (3) timings are based on 66 mhz pbi_clk.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 87 electrical specificationsintel ? 81348 4.5 storage interface electrical specifications table 33. storage interface reference clock electrical characteristics [s_clkp0/ s_clkn0] parameter limit unit condition min. typ. max. s_clkp0/s_clkn0 differential input voltage 250 350 1000 mv diff-pk s_clkp0/s_clkn0 input common mode voltage v cc1p8s 0.665 v cc1p8s 0.7 v cc1p8s 0.735 v s_clkp0/s_clkn0 input bias voltage v cc1p8s /2 - 100 mv v cc1p8s /2 v cc1p8s /2 + 100 mv v this is the voltage to which both s_clkp0/ s_clkn0 are internally biased. s_clkp0/s_clkn0 input clock frequency 150 - 100 ppm 150 150 + 100 ppm mhz 1.5g, 3g 125 - 100 ppm 125 125 + 100 ppm 1g, 1.5g, 2g, 3g, 4g s_clkp0/s_clkn0 duty cycle 45 55 % s_clkp0/s_clkn0 rise and fall ttime 0.35 0.55 ns 20% to 80% s_clkp0/s_clkn0 input jitter 2 ps rms 10 khzC20 mhz bandwidth s_clkp0/s_clkn0 differential input resistance 80 100 120 ? s_clkp0/s_clkn0 differential input capacitance 1.5 pf notes: 1. s_clkp0/s_clkn0 are ac coupled with a 100 nf capacitor. 2. s_clkp0/s_clkn0 are driven from 100 5% ? differential source
intel ? 81348electrical specifications intel ? 81348 i/o processor datasheet december 2007 88 order number: 315038-003us table 34. storage interface transmitter output electrical characteristics [s_txp[7:0] s_txn[7:0] parameter limit unit condition min. typ. max. s_txp [7:0] s_txn [7:0] differential output voltage 400 500 600 mv pk-pk sata gen 1i. gen 1m 800 1600 sata gen 1x, gen 2x 400 700 sata gen 2i, gen 2m 400 1600 sas (including emphasis) s_txp [7:0] s_txn [7:0] de-emphasis 044%see figure 27 on page 88 . s_txp [7:0] s_txn [7:0] differential output rise & fall time 47 130 ps s_txp [7:0] s_txn [7:0] differential output impedance 85 100 115 ? s_txp [7:0] s_txn [7:0] singled ended impedance 40 ? notes: 1. transmitter outputs are ac coupled with a 10 nf capacitor. figure 27. maximum amplitude maximum amplitude de-emphasis: percentage of maximum voltage below maximum one bit (ui) 0 when emphasis is enabled, the de-emphasized output level is defined as a percentage of the maximum voltage below the maximum output level.
intel ? 81348 i/o processor december 2007 datasheet order number: 315038-003us 89 electrical specificationsintel ? 81348 table 35. storage interface receiver input electrical characteristics [s_rxp[7:0] s_rxn[7:0] parameter limit unit condition min. typ. max. s_rxp [7:0] s_rxn [7:0] differential input voltage 325 600 mv pk-pk sata gen 1i 240 600 sata gen 1m 275 1600 sata gen 1x, 2x 275 750 sata gen 2i 240 750 sata gen 2m 275 1600 sas (including emphasis) s_rxp [7:0] s_rxn [7:0] differential input impedance 85 100 115 ? s_rxp [7:0] s_rxn [7:0] common mode impedance 20 30 40 ? notes: 1. receiver inputs are ac coupled with a 10 nf capacitor. figure 28. intel? 81348 i/o processor storage phy 1.2 v/1.8 v power sequencing system requirements signal/ball names concerned: vcc 1p8s, vcc1p2as and vcc1p2ds 1.8v supply should never exceed the 1.2v supply (analog or digital) when vcc1p2 < nominal the 3.3v supplies and vccvio supplies don?t have any sequencing requirements. 0 1.2 1.8 1.8v safe 1.8v safe 1.8v unsafe 1.8v unsafe 0 1.2 1.8 1.8v safe 1.8v safe 1.8v unsafe 1.8v unsafe 1.8v safe 1.8v safe 1.8v unsafe 1.8v unsafe

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